Now showing items 1-3 of 3

  • Cross-layer system reliability assessment framework for hardware faults 

    Vallero, Alessandro; Savino, Alessandro; Politano, Gianfranco; Di Carlo, Stefano; Chatzidimitriou, Athanansios; Tselonis, Sotiris; Kaliorakis, Manolis; Gizipoulos, Dimitris; Riera Villanueva, Marc; Canal Corretger, Ramon; González Colás, Antonio María; Kooli, Maha; Bosio, Alberto; Di Natale, Giorgio (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Open Access
    System reliability estimation during early design phases facilitates informed decisions for the integration of effective protection mechanisms against different classes of hardware faults. When not all system abstraction ...
  • MeRLiN: Exploiting dynamic instruction behavior for fast and accurate microarchitecture level reliability assessment 

    Kaliorakis, Manolis; Gizopoulos, Dimitris; Canal Corretger, Ramon; González Colás, Antonio María (Association for Computing Machinery (ACM), 2017)
    Conference report
    Open Access
    Early reliability assessment of hardware structures using microarchitecture level simulators can effectively guide major error protection decisions in microprocessor design. Statistical fault injection on microarchitectural ...
  • SyRA: early system reliability analysis for cross-layer soft errors resilience in memory arrays of microprocessor systems 

    Vallero, Alessandro; Savino, Alessandro; Chatzidimitriou, Athanansios; Kaliorakis, Manolis; Kooli, Maha; Riera Villanueva, Marc; Di Natale, Giorgio; Bosio, Alberto; Canal Corretger, Ramon; Gizopoulos, Dimitris; Di Carlo, Stefano (Institute of Electrical and Electronics Engineers (IEEE), 2018-01-01)
    Article
    Open Access
    Cross-layer reliability is becoming the preferred solution when reliability is a concern in the design of a microprocessor-based system. Nevertheless, deciding how to distribute the error management across the different ...