Browsing by Author "Jiménez, Daniel A."

Now showing items 1-11 of 11

    • A decoupled KILO-instruction processor 

      Pericàs Gleim, Miquel; Cristal Kestelman, Adrián; González García, Rubén; Jiménez, Daniel A.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2006)
      Conference report
      Open Access
      Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elusive goal. Traditional processors are ...

    • A flexible heterogeneous multi-core architecture 

      Pericàs Gleim, Miquel; Cristal Kestelman, Adrián; Cazorla, Francisco; González García, Rubén; Jiménez, Daniel A.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2007)
      Conference report
      Open Access
      Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a challenge as application mixes in this ...

    • A two level load/store queue based on execution locality 

      Pericàs Gleim, Miquel; Cristal Kestelman, Adrián; Cazorla, Francisco; González García, Rubén; Veidenbaum, Alexander V; Jiménez, Daniel A.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
      Conference report
      Open Access
      Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be increasingly limited by the remaining sequential ...

    • A two level neural approach combining off-chip prediction with adaptive prefetch filtering 

      Jamet, Alexandre Valentin; Vavouliotis, Georgios; Jiménez, Daniel A.; Álvarez Martí, Lluc; Casas, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2024)
      Conference report
      Open Access
      To alleviate the performance and energy overheads of contemporary applications with large data footprints, we propose the Two Level Perceptron (TLP) predictor, a neural mechanism that effectively combines predicting whether ...

    • Characterizing the impact of last-level cache replacement policies on big-data workloads 

      Jamet, Alexandre Valentin; Álvarez Martí, Lluc; Jiménez, Daniel A.; Casas, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Conference report
      Open Access
      The vast disparity between Last Level Cache (LLC) and memory latencies has motivated the need for efficient cache management policies. The computer architecture literature abounds with work on LLC replacement policy. ...

    • Exploiting page table locality for Agile TLB Prefetching 

      Vavouliotis, Georgios; Alvarez Martí, Lluc; Karakostas, Vasileios; Nikas, Konstantinos; Koziris, Nectarios; Jiménez, Daniel A.; Casas, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2021)
      Conference report
      Open Access
      Frequent Translation Lookaside Buffer (TLB) misses incur high performance and energy costs due to page walks required for fetching the corresponding address translations. Prefetching page table entries (PTEs) ahead of ...

    • Machine learning for microarchitectural prediction 

      Jiménez, Daniel A. (Barcelona Supercomputing Center, 2017-09-10)
      Conference report
      Open Access
      Cache replacement and branch prediction are two important microarchitectural prediction techniques for improving performance. We propose a data-driven approach to designing microarchitectural predictors. Through simulation, ...

    • Morrigan: A composite instruction TLB prefetcher 

      Vavouliotis, Georgios; Alvarez Martí, Lluc; Grot, Boris; Jiménez, Daniel A.; Casas, Marc (Association for Computing Machinery (ACM), 2021)
      Conference report
      Open Access
      The effort to reduce address translation overheads has typically targeted data accesses since they constitute the overwhelming portion of the second-level TLB (STLB) misses in desktop and HPC applications. The address ...

    • Page size aware cache prefetching 

      Vavouliotis, Georgios; Chacon, Gino; Álvarez Martí, Lluc; Gratz, Paul V.; Jiménez, Daniel A.; Casas, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2022)
      Conference report
      Open Access
      The increase in working set sizes of contemporary applications outpaces the growth in cache sizes, resulting in frequent main memory accesses that deteriorate system per- formance due to the disparity between processor and ...

    • Practically tackling memory bottlenecks of graph-processing workloads 

      Jamet, Alexandre Valentin; Vavouliotis, Georgios; Jiménez, Daniel A.; Álvarez Martí, Lluc; Casas, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2024)
      Conference report
      Open Access
      Graph-processing workloads have become widespread due to their relevance on a wide range of application domains such as network analysis, path- planning, bioinformatics, and machine learning. Graph-processing workloads ...

    • Sensible energy accounting with abstract metering for multicore systems 

      Liu, Qixiao; Moretó Planas, Miquel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Jiménez, Daniel A.; Valero Cortés, Mateo (2016-01)
      Article
      Open Access
      Chip multicore processors (CMPs) are the preferred processing platform across different domains such as data centers, real-time systems, and mobile devices. In all those domains, energy is arguably the most expensive ...