Browsing by Author "Jalle Ibarra, Javier"
Now showing items 1-7 of 7
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Bus designs for time-probabilistic multicore processors
(European Interactive Digital Advertising Alliance (EDAA), 2014)
Conference report
Restricted access - publisher's policyProbabilistic Timing Analysis (PTA) reduces the amount of information needed to provide tight WCET estimates in real-time systems with respect to classic timing analysis. PTA imposes new requirements on hardware design ... -
Contention-aware performance monitoring counter support for real-time MPSoCs
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference lecture
Open AccessTasks running in MPSoCs experience contention delays when accessing MPSoC’s shared resources, complicating task timing analysis and deriving execution time bounds. Understanding the Actual Contention Delay (ACD) each task ... -
Data bus slicing for contention-free multicore real-time memory systems
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Open AccessMemory access contention is one of the main contributors to tasks' execution time variability in real-Time multicores. Existing techniques to control memory contention based on time-sharing memory access do not scale well ... -
Deconstructing bus access control policies for real-time multicores
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Conference report
Restricted access - publisher's policyMulticores may satisfy the growing performance requirements of critical Real-Time systems which has made industry to consider them for future real-time systems. In a multicore, the bus contention-control policy plays a key ... -
Improving early design stage timing modeling in multicore based real-time systems
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Open AccessThis paper presents a modelling approach for the timing behavior of real-time embedded systems (RTES) in early design phases. The model focuses on multicore processors - accepted as the next computing platform for RTES - ... -
Improving time predictability of shared hardware resources in real-time multicore systems : emphasis on the space domain
(Universitat Politècnica de Catalunya, 2016-07-18)
Doctoral thesis
Open AccessCritical Real-Time Embedded Systems (CRTES) follow a verification and validation process on the timing and functional correctness. This process includes the timing analysis that provides Worst-Case Execution Time (WCET) ... -
Validating a timing simulator for the NGMP multicore processor
(European Space Agency (ESA), 2016)
Conference report
Open AccessTiming simulation is a key element in multicore systems design. It enables a fast and cost effective design space exploration, allowing to simulate new architectural improvements without requiring RTL abstraction levels. ...
