Now showing items 1-7 of 7

  • Bus designs for time-probabilistic multicore processors 

    Jalle Ibarra, Javier; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (European Interactive Digital Advertising Alliance (EDAA), 2014)
    Conference report
    Restricted access - publisher's policy
    Probabilistic Timing Analysis (PTA) reduces the amount of information needed to provide tight WCET estimates in real-time systems with respect to classic timing analysis. PTA imposes new requirements on hardware design ...
  • Contention-aware performance monitoring counter support for real-time MPSoCs 

    Jalle Ibarra, Javier; Fernández, Mikel; Abella, Jaume; Andersson, Jan; Patte, Mathieu; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference lecture
    Open Access
    Tasks running in MPSoCs experience contention delays when accessing MPSoC’s shared resources, complicating task timing analysis and deriving execution time bounds. Understanding the Actual Contention Delay (ACD) each task ...
  • Data bus slicing for contention-free multicore real-time memory systems 

    Jalle Ibarra, Javier; Quiñones, Eduardo; Abella, Jaume; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Open Access
    Memory access contention is one of the main contributors to tasks' execution time variability in real-Time multicores. Existing techniques to control memory contention based on time-sharing memory access do not scale well ...
  • Deconstructing bus access control policies for real-time multicores 

    Jalle Ibarra, Javier; Abella Ferrer, Jaume; Quiñones, Eduardo; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
    Conference report
    Restricted access - publisher's policy
    Multicores may satisfy the growing performance requirements of critical Real-Time systems which has made industry to consider them for future real-time systems. In a multicore, the bus contention-control policy plays a key ...
  • Improving early design stage timing modeling in multicore based real-time systems 

    Trilla, David; Jalle Ibarra, Javier; Fernández, Mikel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Open Access
    This paper presents a modelling approach for the timing behavior of real-time embedded systems (RTES) in early design phases. The model focuses on multicore processors - accepted as the next computing platform for RTES - ...
  • Improving time predictability of shared hardware resources in real-time multicore systems : emphasis on the space domain 

    Jalle Ibarra, Javier (Universitat Politècnica de Catalunya, 2016-07-18)
    Doctoral thesis
    Open Access
    Critical Real-Time Embedded Systems (CRTES) follow a verification and validation process on the timing and functional correctness. This process includes the timing analysis that provides Worst-Case Execution Time (WCET) ...
  • Validating a timing simulator for the NGMP multicore processor 

    Jalle Ibarra, Javier; Abella Ferrer, Jaume; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (European Space Agency (ESA), 2016)
    Conference report
    Open Access
    Timing simulation is a key element in multicore systems design. It enables a fast and cost effective design space exploration, allowing to simulate new architectural improvements without requiring RTL abstraction levels. ...