Now showing items 1-2 of 2

    • Analysis and optimization of a debug post-silicon hardware architecture 

      Sanchez Moreno, Joel (Universitat Politècnica de Catalunya, 2022-01-24)
      Master thesis
      Restricted access - confidentiality agreement
      The goal of this thesis is to analyze the post-silicon validation hardware infrastructure implemented on multicore systems taking as an example Esperanto Technologies SoC, which has thousands of RISC-V processors and targets ...
    • NoC Topology synthesis using metaheuristics 

      Solà Montserrat, Jordi (Universitat Politècnica de Catalunya, 2020-06-26)
      Master thesis
      Open Access
      In this project, we have studied the potential of hybrid metaheuristics at synthesizing network on chip topologies. We make the case that the problem can be split in three sub-problems, each solved by a different metaheuristic ...