Now showing items 1-20 of 203

    • 2 transistors + 2 diodes-based PEBB designed for general applications in power electronics 

      Nicolás Apruzzese, Joan; Rocabert Delgado, Joan; Bordonau Farrerons, José; Busquets Monge, Sergio; Alepuz Menéndez, Salvador; Martínez Velasco, Juan Antonio; Peracaula Roura, Joan (2009)
      Conference lecture
      Open Access
      This paper presents a new Power Electronic Building Block (PEBB) designed to facilitate the implementation of different power converter topologies. The proposed PEBB consists of two diodes and two transistors and it can ...
    • 3D-printed UHF-RFID tag for embedded applications 

      Vidal, Neus; Lopez-Villegas, Josep Maria; Romeu Robert, Jordi; Salas Barenys, Arnau; Garcia-Miquel, Aleix; González López, Giselle; Jofre Roca, Lluís (Institute of Electrical and Electronics Engineers (IEEE), 2020-08-10)
      Article
      Open Access
      This paper presents the design, manufacture and characterization of a novel 3D passive UHF-RFID tag for embedded applications. The prototype is fabricated using additive manufacturing techniques: 3D printing and copper ...
    • 5GHz CMOS all-pass filter-based true time delay cell 

      Aghazadeh, Seyed Rasoul; Martínez García, Herminio; Saberkari, Alireza (2018-12-22)
      Article
      Open Access
      Analog CMOS time-delay cells realized by passive components, e.g., lumped LC delay lines, are inefficient in terms of area for multi-GHz frequencies. All-pass filters considered as active circuits can, therefore, be the ...
    • A 56-GHz LC-Tank VCO With 17% tuning range in 65-nm bulk CMOS for wireless HDMI 

      González Jiménez, José Luis; Badets, Franck; Martineau, Baudouin; Belot, Didier (2010-03-25)
      Article
      Open Access
      A voltage-controlled oscillator (VCO) with a central frequency of 56 GHz and a 17% tuning range is presented. The oscillation frequency is tuned both by an analog input and by a 3-bit digital control bus using the same ...
    • A case study for the verification of complex timed circuits: IPCMOS 

      Peña Basurto, Marco Antonio; Cortadella, Jordi; Pastor Llorens, Enric; Smirnov, Alexandre (Institute of Electrical and Electronics Engineers (IEEE), 2002)
      Conference report
      Open Access
      The verification of a n-stage pulse-driven IPCMOS pipeline, for any n>0, is presented. The complexity of the system is 32n transistors and delay information is provided at the level of transistor The correctness of the ...
    • A compact switched-capacitor multi-bit quantizer for low-power high-resolution delta-sigma ADCs 

      Cisneros Fernández, Jose Agustín; Serra Graells, Francisco; Teres Teres, Lluis; Dei, Michele (Institute of Electrical and Electronics Engineers (IEEE), 2018)
      Conference lecture
      Restricted access - publisher's policy
      This paper proposes a compact switched-capacitor (SC) multi-bit flash quantizer for low-power high-resolution delta-sigma modulators (¿SMs). First, a general power model for single-loop ¿SMs is presented to show the ...
    • A comparison of PUF cores suitable for FPGA devices 

      Mureddu, Ugo; Bossuet, Lilian; Fischer, Viktor (2016-11-14)
      Conference report
      Open Access
      A PUF extracts a unique identifier per die using physical random variation caused by variability of the manufacturing process. PUFs can be used for hardware authentication, but also as generators of confidential keys. ...
    • A comprehensive high-level model for CMOS-MEMS resonators 

      Banerji, Saoni; Fernández, Daniel; Madrenas Boadas, Jordi (2018-01-24)
      Article
      Open Access
      This paper presents a behavioral modeling technique for CMOS microelectromechanical systems (MEMS) microresonators that enables simulation of an MEMS resonator model in Analog Hardware Description Language format within a ...
    • A crosstalk latch circuit design 

      Rubio Sola, Jose Antonio; Pons Nin, Joan; Anglada, Raimon (Institute of Electrical and Electronics Engineers (IEEE), 1990)
      Conference report
      Restricted access - publisher's policy
      A D-latch sequential circuit design is presented that exhibits an elevated degree of tolerance to common and differential mode noise in the clock lines. The circuit tolerates noise voltages in the clock signals in the range ...
    • A detailed methodology to compute soft error rates in advanced technologies 

      Riera Villanueva, Marc; Canal Corretger, Ramon; Abella Ferrer, Jaume; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference report
      Restricted access - publisher's policy
      System reliability has become a key design aspect for computer systems due to the aggressive technology miniaturization. Errors are typically dominated by transient faults due to radiation and are strongly related to the ...
    • A forming-free ReRAM cell with low operating voltage 

      Yang, Binbin; Xu, Nuo; Li, Cheng; Huang, Chenglong; Ma, Desheng; Liu, Jiahao; Arumi Delgado, Daniel; Fang, Liang (2020-11-25)
      Article
      Open Access
      The unwanted electro-forming process is unavoidable for the practical application of most resistive random access memory (ReRAM) devices, which is always being one of the obstacles for the massive commercialization of this ...
    • A highly-accurate low-power CMOS potentiostat for implantable biosensors 

      Razzaghpour, Milad; Rodriguez Duenas, Saul; Alarcón Cot, Eduardo José; Rusu, Ana (IEEE, 2011)
      Conference report
      Restricted access - publisher's policy
      Current-mirror-based potentiostats suffer from systematic and random errors causing offset, gain and linearity error in reading out the sensor data. In this work, a new potentiostat topology is proposed to eliminate the ...
    • A highly-repeatable, broadband 180º phase switch for integrated MEMS processes 

      Llamas Morote, Marco Antonio; Girbau Sala, David; Ribó, M.; Pradell i Cara, Lluís; Giacomozzi, Flavio; Colpo, S.; Coccetti, Favio; Aouba, Stephane (2011)
      Conference report
      Restricted access - publisher's policy
      A broadband 0º/180º phase switch based on a slotline-coplanar-waveguide cross loaded with two MEMS switches in opposed (ON/OFF or OFF/ON) states, is reported. The fabrication was made on high-resistivity silicon substrates ...
    • A Low-Cost Unified Experimental FPGA Board for Cryptography Applications 

      Bartík, Matěj; Buček, Jiří (2016-11-16)
      Conference report
      Open Access
      This paper describes the evaluation of available experimental boards, the comparison of their supported set of experiments and other aspects. The second part of this evaluation is focused on the design process of the ...
    • A multi-synchronous bi-directional NoC (MBiNoC) architecture with dynamic self-reconfigurable channel for the GALS infrastructure 

      Kamal, Rajeev; Moreno Aróstegui, Juan Manuel (Elsevier, 2017-03-16)
      Article
      Open Access
      Abstract To enhance the performance of on-chip communications of Globally Asynchronous Locally Synchronous Systems (GALS), a dynamic reconfigurable multi-synchronous router architecture is proposed to increase network on ...
    • A novel tunable multimodal bandpass filter 

      Contreras Lizarraga, Adrián Arturo; Pradell i Cara, Lluís; Ribó, M. (2011)
      Conference report
      Restricted access - publisher's policy
      This paper presents a novel uniplanar tunable bandpass filter. In this filter, each resonator can be reconfigured easily using PIN diodes or MEMS switches. Design equations are derived from a simple circuit model which ...
    • A pragmatic gaze on stochastic resonance based variability tolerant memristance 

      Ntinas, Vasileios; Rubio Sola, Jose Antonio; Sirakoulis, Georgios Ch.; Cotofana, Sorin (Institute of Electrical and Electronics Engineers (IEEE), 2019)
      Conference report
      Open Access
      Stochastic Resonance (SR) is a nonlinear system specific phenomenon, which was demonstrated to lead to system unexpected (counter-intuitive) performance improvements under certain noise conditions. Memristor, on the other ...
    • A Reliable Low-area Low-power PUF-based Key Generator 

      Böhm, Christoph; Bucci, Marco; Hofer, Maximilian; Luzzi, Raimondo (2016-11-14)
      Conference report
      Open Access
      This paper reports the implementation of a lowarea low-power 128-bit PUF-based key generation module which exploits a novel Two-Stage IDentification (TSID) cell showing a higher noise immunity then a standard SRAM cell. ...
    • A Self-Repairable TRNG 

      Martin, Honorio; Di Natale, Giorgio; Peris-Lopez, Pedro (2016-11-14)
      Conference report
      Open Access
    • A systematic method to design efficient ternary high performance CNTFET-based logic cells 

      Dabaghi Zarandi, Arezoo; Reza Reshadinezhad, Mohammad; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2020-01-01)
      Article
      Open Access
      The huge quantity of nodes and interconnections in modern binary circuits leads to extremely high levels of energy consumption. The interconnection complexity and other issues of binary circuits encourage researchers to ...