Now showing items 1-20 of 23

    • A new look at the conditions for the synthesis of speed-independent circuits 

      Pastor Llorens, Enric; Cortadella, Jordi; Roig Mansilla, Oriol (Institute of Electrical and Electronics Engineers (IEEE), 1995)
      Conference report
      Open Access
      This paper presents a set of sufficient conditions for the gate-level synthesis of speed-independent circuits when constrained to a given class of gate library. Existing synthesis methodologies are restricted to architectures ...
    • A new probabilistic design methodology of nanoscale digital circuits 

      García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
      Conference report
      Restricted access - publisher's policy
      The continuing trends of device scaling and increase in complexity towards terascale system on chip level of integration are putting growing difficulties into several areas of design. The intrinsic variability problem is ...
    • A retargetable and accurate methodology for logic-IP-internal electromigration assessment 

      Jain, Palkesh; Sapatnekar, Sachin S.; Cortadella, Jordi (2015)
      Conference report
      Open Access
      A new methodology for SoC-level logic-IP-internal EM verification is presented, which provides an on-the-fly retargeting capability for reliability constraints. This flexibility is available at the design verification ...
    • An integrated vector-scalar design on an in-order ARM core 

      Stanic, Milan; Palomar Pérez, Óscar; Hayes, Timothy; Ratkovic, Ivan; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Valero Cortés, Mateo (2017-07)
      Article
      Open Access
      In the low-end mobile processor market, power, energy, and area budgets are significantly lower than in the server/desktop/laptop/high-end mobile markets. It has been shown that vector processors are a highly energy-efficient ...
    • Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2010)
      Conference report
      Restricted access - publisher's policy
      With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits. Propagation delays which decide circuit ...
    • Curvature of BEOL cantilevers in CMOS-MEMS processes 

      Valle, Juan José; Fernández Martínez, Daniel; Madrenas Boadas, Jordi; Barrachina, Laura (2017-08-01)
      Article
      Open Access
      This paper presents the curvature characterization results of released back-end-of-line 5 µm-wide cantilevers for two different 0.18-µm 1P6M complementary metal-oxide semiconductor microelectromechanical systems processes. ...
    • Desarrollo de una Aplicación Informática para el Diseño y Estudio del circuito Steinmetz 

      Caro Huertas, Eduardo (Universitat Politècnica de Catalunya, 2007-05)
      Master thesis (pre-Bologna period)
      Open Access
      El circuito Steinmetz consiste en la conexión de dos reactancias (normalmente una bobina y un condensador) en triángulo con una carga monofásica, con el objeto de simetrizar las intensidades consumidas por el conjunto. El ...
    • Desynchronization: Synthesis of asynchronous circuits from synchronous specifications 

      Cortadella, Jordi; Kondratyev, Alex; Lavagno, Luciano; Sotiriou, Christos (2006-10)
      Article
      Open Access
      Asynchronous implementation techniques, which measure logic delays at runtime and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst case delays at design ...
    • Diseño de circuitos y sistemas integrados 

      Rubio, Antonio; Altet Sanahujes, Josep; Aragonès Cervera, Xavier; González Jiménez, José Luis; Mateo Peña, Diego; Moll Echeto, Francisco de Borja (Edicions UPC, 2003)
      Book
      Restricted access to UB, UAB, UPC, UPF, UdG, UdL, URV, UOC, BC, UVic, UJI, URL, UIC users
      La tecnología de circuitos integrados, basada principalmente en la miniaturización de los circuitos ha evolucionado intensamente en los últimos tiempos. El objetivo de esta obra es dar a conocer esta evolución reciente y ...
    • Elastic circuits 

      Carmona Vargas, Josep; Cortadella, Jordi; Kishinevsky, Michael; Taubin, Alexander (2009-10)
      Article
      Open Access
      Elasticity in circuits and systems provides tolerance to variations in computation and communication delays. This paper presents a comprehensive overview of elastic circuits for those designers who are mainly familiar with ...
    • Exploiting the locality of memory references to reduce the address bus energy 

      Musoll Cinca, Enric; Lang, Tomás; Cortadella, Jordi (Association for Computing Machinery (ACM), 1997)
      Conference report
      Open Access
      The energy consumption at the I/O pins is a significant part of the overall chip consumption. This paper presents a method for encoding an external address bus which lowers its activity and, thus, decreases the energy. ...
    • Fundamentos de diseño microelectrónico 

      Castañer Muñoz, Luis María; Jiménez Serres, Vicente; Bardés Llorensí, Daniel (Edicions UPC, 2002)
      Book
      Restricted access to UB, UAB, UPC, UPF, UdG, UdL, URV, UOC, BC, UVic, UJI, URL, UIC users
      El presente texto aporta el material necesario para un curso introductorio de diseño microelectrónico. Este libro está concebido como una herramienta de autoaprendizaje y, por ello, en cada capítulo se proponen numerosos ...
    • iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Conference report
      Open Access
      Negative bias temperature instability (NBTI) is a major cause of concern for chip designers because of its inherent ability to drastically reduce silicon reliability over the lifetime of the processor. Coupled with statistical ...
    • MInGLE: An efficient framework for domain acceleration using low-power specialized functional units 

      González Álvarez, Cecilia Noemí; Sartor, Jennifer B.; Álvarez Martínez, Carlos; Jiménez González, Daniel; Eeckhout, Lieven (2016-06)
      Article
      Open Access
      The end of Dennard scaling leads to new research directions that try to cope with the utilization wall in modern chips, such as the design of specialized architectures. Processor customization utilizes transistors more ...
    • MODEST: a model for energy estimation under spatio-temporal variability 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2010)
      Conference report
      Restricted access - publisher's policy
      Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of the changing operating and environmental ...
    • Narrowing the margins with elastic clocks 

      Cortadella, Jordi; Lavagno, Luciano; Amiri, Djavad; Casanova Bachs, Jonàs; Macián, Carlos; Martorell, Ferran; Moya, Juan A.; Necchi, Luca; Sokolov, Danil; Tuncer, Emre (Institute of Electrical and Electronics Engineers (IEEE), 2010)
      Conference report
      Open Access
      The continuous shrinking of process geometries increases variability and demands for conservative margins that have a negative impact on performance. With conventional clocks, the cycle period has to be defined to accommodate ...
    • Physical-aware link allocation and route assignment for chip multiprocessing 

      Nikitin, Nikita; Chatterjee, Satrajit; Cortadella, Jordi; Kishinevsky, Michael; Ogras, Umit (Institute of Electrical and Electronics Engineers (IEEE), 2010)
      Conference report
      Open Access
      The architecture definition, design, and validation of the interconnect networks is a key step in the design of modern on-chip systems. This paper proposes a mathematical formulation of the problem of simultaneously defining ...
    • Robustness to voltage noise with ring oscillator clocks 

      Machado, Lucas; Roca Pérez, Antoni; Cortadella, Jordi (2019-04)
      Article
      Open Access
      Voltage noise is the main source of dynamic variability in integrated circuits and a major concern for the design of power delivery networks (PDNs). Lower supply voltages were made possible with technology scaling, but ...
    • RTL-aware dataflow-driven macro placement 

      Vidal Obiols, Alexandre; Cortadella, Jordi; Petit Silvestre, Jordi; Galcerán Oms, Marc; Martorell Cid, Ferran (Institute of Electrical and Electronics Engineers (IEEE), 2019)
      Conference report
      Open Access
      When RTL designers define the hierarchy of a system, they exploit their knowledge about the conceptual abstractions devised during the design and the functional interactions between the logical components. This valuable ...
    • Symbolic performance analysis of elastic systems 

      Galcerán Oms, Marc; Cortadella, Jordi; Kishinevsky, Michael (Institute of Electrical and Electronics Engineers (IEEE), 2010)
      Conference report
      Open Access
      Elastic systems, either synchronous or asynchronous, can be optimized for the average-case performance when they have units with early evaluation or variable latency. The performance evaluation of such systems using ...