Now showing items 1-6 of 6

    • A fault-tolerant last level cache for CMPs operating at ultra-low voltage 

      Ferrerón, Alexandra; Alastruey, Jesús; Suárez Gracía, Dario; Monreal Arnal, Teresa; Ibáñez Marín, Pablo Enrique; Viñals Yúfera, Víctor (Elsevier, 2019-03)
      Article
      Restricted access - publisher's policy
      Voltage scaling to values near the threshold voltage is a promising technique to hold off the many-core power wall. However, as voltage decreases, some SRAM cells are unable to operate reliably and show a behavior consistent ...
    • Gestión de contenidos en caches operando a bajo voltaje 

      Ferrerón, Alexandra; Alastruey, Jesús; Suárez Gracía, Dario; Monreal Arnal, Teresa; Ibáñez Marín, Pablo Enrique; Viñals Yúfera, Víctor (2016)
      Conference report
      Open Access
      La eficiencia energética de las caches en chip puede mejorarse reduciendo su voltaje de alimentación (Vdd ). Sin embargo, este escalado de Vdd está limitado a una tensión Vddmin por debajo de la cual algunas celdas SRAM ...
    • ReD: A policy based on reuse detection for demanding block selection in last-level Caches 

      Díaz Maag, Javier; Ibáñez Marín, Pablo Enrique; Monreal Arnal, Teresa; Viñals Yúfera, Víctor; Llaberia Griñó, José M. (2017)
      Conference report
      Open Access
      In this paper, we propose a new block selection policy for Last-Level Caches (LLCs) that decides, based on Reuse Detection, whether a block coming from main memory is inserted, or not, in the LLC. The proposed policy, ...
    • ReD: A reuse detector for content selection in exclusive shared last-level caches 

      Díaz, Javier; Monreal Arnal, Teresa; Ibáñez Marín, Pablo Enrique; Llaberia Griñó, José M.; Viñals Yúfera, Víctor (Elsevier, 2019-03)
      Article
      Restricted access - publisher's policy
      The reference stream reaching a chip multiprocessor Shared Last-Level Cache (SLLC) shows poor temporal locality, making conventional cache management policies inefficient. Few proposals address this problem for exclusive ...
    • Reuse Detector: improving the management of STT-RAM SLLCs 

      Rodríguez Rodríguez, Roberto; Díaz Maag, Javier; Castro, Fernando; Ibáñez Marín, Pablo Enrique; Chaver Martínez, Daniel A.; Viñals Yúfera, Víctor; Sáez Alcaide, Juan Carlos; Prieto Matías, Manuel; Piñuel, Luis; Monreal Arnal, Teresa; Llaberia Griñó, José M. (2018-06-01)
      Article
      Open Access
      Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-Transfer Torque RAM (STT-RAM) is currently ...
    • Selección de contenidos basada en reuso para caches compartidas en exclusión 

      Díaz Maag, Javier; Monreal Arnal, Teresa; Viñals Yúfera, Víctor; Ibáñez Marín, Pablo Enrique; Llaberia Griño, José María (2015)
      Conference report
      Open Access
      Publicaciones previas revelan que el flujo de referencias que llega a la cache compartida (SLLC) de un chip multiprocesador muestra poca localidad temporal. Sin embargo, muestra localidad de reuso, es decir, los bloques ...