Now showing items 1-16 of 16

  • 1st BSC Doctoral Symposium : book of abstracts 

    Cucchietti, Fernando; Comes, Carles; Badia Moragas, Alba; Cabeza, Israel; Eguzkitza, Beatriz; Gifre Renom, Lluís; González, Santiago; Guevara, Marc; Hernández, Roger; Hussain, Tassadaq; Jiménez, Brian; Liu, Qixiao; Moal, Iain; Obiso, Vincenzo; Palavedu, Karthikeyan; Panic, Milos; Rajovic, Nikola; Royuela, Sara; Scaini, Chiara; Soret, Albert; Stipić, Srđjan; Strassburg, Janko; Valverde, Víctor; Villalba, Álvaro (Barcelona Supercomputing Center, 2014-05-26)
    Conference report
    Open Access
  • Advanced pattern based memory controller for FPGA based HPC applications 

    Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
    Restricted access - publisher's policy
    The ever-increasing complexity of high-performance computing applications limits performance due to memory constraints in FPGAs. To address this issue, we propose the Advanced Pattern based Memory Controller (APMC), which ...
  • AMC: Advanced Multi-accelerator Controller 

    Hussain, Tassadaq; Haider, Amna; Gursal, Shakaib A.; Ayguadé Parra, Eduard (2015-01)
    Article
    Open Access
    The rapid advancement, use of diverse architectural features and introduction of High Level Synthesis (HLS) tools in FPGA technology have enhanced the capacity of data-level parallelism on a chip. A generic FPGA based HLS ...
  • AMMC: advance multi-core memory controller 

    Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference lecture
    Open Access
    In this work, we propose an efficient scheduler and intelligent memory manager known as AMMC (Advanced Multi-Core Memory Controller), which proficiently handles data movement and computational tasks. The proposed AMMC ...
  • A novel access pattern-based multi-core memory architecture 

    Hussain, Tassadaq (Universitat Politècnica de Catalunya, 2014-12-18)
    Doctoral thesis
    Open Access
    Increasingly High-Performance Computing (HPC) applications run on heterogeneous multi-core platforms. The basic reason of the growing popularity of these architectures is their low power consumption, and high throughput ...
  • EMVS: Embedded Multi Vector-core System 

    Hussain, Tassadaq; Haider, Amna; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard (2018-06)
    Article
    Restricted access - publisher's policy
    With the increase in the density and performance of digital electronics, the demand for a power-efficient high-performance computing (HPC) system has been increased for embedded applications. The existing embedded HPC ...
  • MAPC: memory access pattern based controller 

    Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
    Restricted access - publisher's policy
    Traditionally, system designers have attempted to improve system performance by scheduling the processing cores and by exploring different memory system configurations and there is comparatively less work done scheduling ...
  • MAPC: memory access pattern based controller 

    Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
    Restricted access - publisher's policy
    Traditionally, system designers have attempted to improve system performance by scheduling the processing cores and by exploring different memory system configurations and there is comparatively less work done scheduling ...
  • Memory controller for vector processor 

    Hussain, Tassadaq; Palomar, Oscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard (Springer, 2018-11)
    Article
    Open Access
    To manage power and memory wall affects, the HPC industry supports FPGA reconfigurable accelerators and vector processing cores for data-intensive scientific applications. FPGA based vector accelerators are used to increase ...
  • PAMS: pattern aware memory system for embedded systems 

    Hussain, Tassadaq; Sönmez, Nehir; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo; Gursal, Shakaib A. (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Conference report
    Open Access
    In this paper, we propose a hardware mechanism for embedded multi-core memory system called Pattern Aware Memory System (PAMS). The PAMS supports static and dynamic data structures using descriptors and specialized memory ...
  • PMSS: a programmable memory system and scheduler for complex memory patterns 

    Hussain, Tassadaq; Haider, Amna; Ayguadé Parra, Eduard (2014-10)
    Article
    Restricted access - publisher's policy
    HPC industry demands more computing units on FPGAs, to enhance the performance by using task/data parallelism. FPGAs can provide its ultimate performance on certain kernels by customizing the hardware for the applications. ...
  • PVMC: Programmable Vector Memory Controller 

    Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
    Open Access
    In this work, we propose a Programmable Vector Memory Controller (PVMC), which boosts noncontiguous vector data accesses by integrating descriptors of memory patterns, a specialized local memory, a memory manager in hardware, ...
  • Reconfigurable memory controller with programmable pattern support 

    Hussain, Tassadaq; Pericas, Miquel; Ayguadé Parra, Eduard (2011)
    Conference report
    Restricted access - publisher's policy
    Heterogeneous architectures are increasingly popular due to their flexibility and high performance per watt capability. A kind of heterogeneous architecture, reconfigurable systems-on-chip, offer high performance per watt ...
  • Stand-alone memory controller for graphics system 

    Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo; Haider, Amna (Springer, 2014)
    Conference report
    Restricted access - publisher's policy
    There has been a dramatic increase in the complexity of graphics applications in System-on-Chip (SoC) with a corresponding increase in performance requirements. Various powerful and expensive platforms to support graphical ...
  • The journey of supercomputing in Pakistan by Dr. Tassadaq Hussain 

    Hussain, Tassadaq (Barcelona Supercomputing Center, 2019)
    Other
    Open Access
  • ViPS: Visual processing system for medical imaging 

    Hussain, Tassadaq; Palomar, Oscar; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Haider, Amna (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Conference report
    Open Access
    Imaging has become an indispensable tool in modern medicine. Various powerful and expensive platforms to study medical imaging applications appear in recent years. In this article, we design and propose a Visual Processing ...