Now showing items 1-20 of 24

  • Adapting TDMA arbitration for measurement-based probabilistic timing analysis 

    Panic, Milos; Abella, Jaume; Quiñones, Eduardo; Hernandez, Carles; Ungerer, Theo; Cazorla, Francisco J. (Elsevier, 2017-07)
    Article
    Restricted access - publisher's policy
    Critical Real-Time Embedded Systems require functional and timing validation to prove that they will perform their functionalities correctly and in time. For timing validation, a bound to the Worst-Case Execution Time ...
  • Aging Assessment and Design Enhancement of Randomized Cache Memories 

    Trilla, David; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. (Institute of Electrical and Electronics Engineers (IEEE), 2017-01-17)
    Article
    Open Access
    Critical real-time systems require the estimation of the worst-case execution time (WCET) for scheduling purposes and resource budgeting. Measurement-based probabilistic timing analysis (MBPTA) has been shown recently as ...
  • Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification 

    Espinosa, Jaime; Hernandez, Carles; Abella, Jaume; de Andres, David; Ruiz, Juan C. (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Conference report
    Open Access
    Increasingly complex microcontroller designs for safety-relevant automotive systems require the adoption of new methods and tools to enable a cost-effective verification of their robustness. In particular, costs associated ...
  • Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis 

    Slijepcevic, Mladen; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. (IEEE, 2017-09-28)
    Conference lecture
    Open Access
    Wormhole-based NoCs (wNoCs) are widely accepted in high-performance domains as the most appropriate solution to interconnect an increasing number of cores in the chip. However, wNoCs suitability in the context of critical ...
  • Cache side-channel attacks and time-predictability in high-performance critical real-time systems 

    Trilla, David; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. (Association for Computing Machinery (ACM), 2018-06-24)
    Conference lecture
    Open Access
    Embedded computers control an increasing number of systems directly interacting with humans, while also manage more and more personal or sensitive information. As a result, both safety and security are becoming ubiquitous ...
  • Characterizing fault propagation in safety-critical processor designs 

    Espinosa, Jaime; Hernandez, Carles; Abella, Jaume (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Conference report
    Open Access
    Achieving reduced time-to-market in modern electronic designs targeting safety critical applications is becoming very challenging, as these designs need to go through a certification step that introduces a non-negligible ...
  • Design and implementation of a fair credit-based bandwidth sharing scheme for buses 

    Slijepcevic, Mladen; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. (Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
    Conference lecture
    Open Access
    Fair arbitration in the access to hardware shared resources is fundamental to obtain low worst-case execution time (WCET) estimates in the context of critical real-time systems, for which performance guarantees are essential. ...
  • Design and integration of hierarchical-placement multi-level caches for real-Time systems 

    Benedicte Illescas, Pedro; Hernandez, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Conference report
    Restricted access - publisher's policy
    Enabling timing analysis in the presence of caches has been pursued by the real-Time embedded systems (RTES) community for years due to cache's huge potential to reduce software's worst-case execution time (WCET). However, ...
  • Design and integration of hierarchical-placement multi-level caches for real-time systems 

    Benedicte, Pedro; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. (IEEE, 2018-04-23)
    Conference lecture
    Open Access
    Enabling timing analysis in the presence of caches has been pursued by the real-time embedded systems (RTES) community for years due to cache's huge potential to reduce software's worst-case execution time (WCET). However, ...
  • DIMP: A low-cost diversity metric based on circuit path analysis 

    Alcaide, Sergi; Hernandez, Carles; Roca, Antoni; Abella, Jaume (2017)
    Conference report
    Diversity has been regarded as a desirable property of redundant instances, since it allows circuits to behave differently in front of a given fault. However, while qualitatively diversity is a well-understood concept, ...
  • Fitting Software Execution-Time Exceedance into a Residual Random Fault in ISO-26262 

    Agirre, Irune; Cazorla, Francisco J.; Abella, Jaume; Hernandez, Carles; Mezzetti, Enrico; Azkarate-askasua, Mikel; Vardanega, Tullio (IEEE, 2018-09-01)
    Open Access
    Car manufacturers relentlessly replace or augment the functionality of mechanical subsystems with electronic components. Most such subsystems (e.g., steer-by-wire) are safety related, hence, subject to regulation. ISO-26262, ...
  • High-Integrity GPU Designs for Critical Real-Time Automotive Systems 

    Alcaide, Sergi; Kosmidis, Leonidas; Hernandez, Carles; Abella, Jaume (2019)
    Conference lecture
    Open Access
    Autonomous Driving (AD) imposes the use of highperformance hardware, such as GPUs, to perform object recognition and tracking in real-time. However, differently to the consumer electronics market, critical real-time AD ...
  • MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding 

    Díaz, Enrique; Fernández, Mikel; Kosmidis, Leonidas; Mezzetti, Enrico; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. (Springer International Publishing, 2017-05-30)
    Conference lecture
    Open Access
    In critical domains, reliable software execution is increasingly involving aspects related to the timing dimension. This is due to the advent of high-performance (complex) hardware, used to provide the rising levels of ...
  • Modeling RTL Fault Models Behavior to Increase the Confidence on TSIM-based Fault Injection 

    Espinosa, Jaime; Hernandez, Carles; Abella, Jaume (Institute of Electrical and Electronics Engineers (IEEE), 2016-07-04)
    Conference lecture
    Open Access
    Future high-performance safety-relevant applications require microcontrollers delivering higher performance than the existing certified ones. However, means for assessing their dependability are needed so that they can be ...
  • Modelling bus contention during system early design stages 

    Trilla, David; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. (IEEE, 2017-07-31)
    Conference lecture
    Open Access
    Reliably upperbounding contention in multicore shared resources is of prominent importance in the early design phases of critical real-time systems to properly allocate time budgets to applications. However, during early ...
  • On the suitability of time-randomized processors for secure and reliable high-performance computing 

    Trilla, David; Hernandez, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Barcelona Supercomputing Center, 2017-05-04)
    Conference report
    Open Access
    Time-randomized processor (TRP) architectures have been shown as one of the most promising approaches to deal with the overwhelming complexity of the timing analysis of high complex processor architectures for safety-related ...
  • Probabilistic timing analysis on time-randomized platforms for the space domain 

    Fernandez, Mikel; Morales, David; Kosmidis, Leonidas; Bardizbanyan, Alen; Broster, Ian; Hernandez, Carles; Quiñones, Eduardo; Abella, Jaume; Cazorla, Francisco; Machado, Paulo; Fossati, Luca (Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
    Conference lecture
    Open Access
    Timing Verification is a fundamental step in real-time embedded systems, with measurement-based timing analysis (MBTA) being the most common approach used to that end. We present a Space case study on a real platform that ...
  • PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis 

    Cazorla, Francisco J.; Abella, Jaume; Andersson, Jan; Vardanega, Tullio; Vatrinet, Francis; Bate, Iain; Broster, Ian; Azkarate-askasua, Mikel; Wartel, Franck; Cucu, Liliana; Cros, Fabrice; Farrall, Glenn; Gogonel, Adriana; Gianarro, Andrea; Triquet, Benoit; Hernandez, Carles; Lo, Code; Maxim, Cristian; Morales, David; Quiñones, Eduardo; Mezzetti, Enrico; Kosmidis, Leonidas; Aguirre, Irune; Fernandez, Mikel; Slijepcevic, Mladen; Conmy, Philippa; Talaboulma, Walid (IEEE, 2016-08-31)
    Conference lecture
    Open Access
    The use of increasingly complex hardware and software platforms in response to the ever rising performance demands of modern real-time systems complicates the verification and validation of their timing behaviour, which ...
  • Reconciling Time Predictability and Performance in Future Computing Systems 

    Cazorla, Francisco J.; Abella, Jaume; Mezzetti, Enrico; Hernandez, Carles; Vardanega, Tullio; Bernat, Guillem (IEEE, 2018-04)
    Article
    Open Access
    MBTA studies the system’s timing in analysis scenarios, to determine upper bounds to the worst-case execution-time behavior that may occur at operation. MBTA’s challenge is to construct analysis-time scenarios that help ...
  • RPR: a random replacement policy with limited pathological replacements 

    Benedicte, Pedro; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. (Association for Computing Machinery (ACM), 2018-04-13)
    Conference lecture
    Open Access
    Measurement-Based Probabilistic Timing Analysis (MBPTA) has consolidated as a technique to estimate probabilistic Worst-Case Execution Times (WCET) for critical software running on processors with high-performance hardware ...