Now showing items 1-12 of 12

  • A dynamic scheduler for balancing HPC applications 

    Boneti, Carlos; Gioiosa, Roberto; Cazorla, Francisco; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Conference report
    Open Access
    Load imbalance cause significant performance degradation in High Performance Computing applications. In our previous work we showed that load imbalance can be alleviated by modern MT processors that provide mechanisms for ...
  • Balancing HPC applications through smart allocation of resources in MT processors 

    Boneti, Carlos; Gioiosa, Roberto; Cazorla, Francisco; Corbalán González, Julita; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Conference report
    Open Access
    Many studies have shown that load imbalancing causes significant performance degradation in High Performance Computing (HPC) applications. Nowadays, Multi-Threaded (MT1) processors are widely used in HPC for their good ...
  • CPU accounting in CMP processors 

    Luque, Carlos; Moreto Planas, Miquel; Cazorla, Francisco; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortés, Mateo (2009-01)
    Article
    Open Access
    Chip-MultiProcessors (CMP) introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is ...
  • ITCA: Inter-Task Conflict-Aware CPU accounting for CMP 

    Luque, Carlos; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Valero Cortés, Mateo (2010)
    Conference report
    Open Access
    Chip-MultiProcessors (CMP) introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is ...
  • ITCA: Inter-Task Conflict-Aware CPU accounting for CMPs 

    Luque, Carlos; Moreto Planas, Miquel; Cazorla, Francisco; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortés, Mateo (IEEE Computer Society, 2009)
    Conference report
    Open Access
    Chip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism from an application. CMPs introduce complexities ...
  • ITCA: inter-task conflict-aware CPU accounting for CMPs 

    Luque, Carlos; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortés, Mateo (IEEE Computer Society Publications, 2009)
    Conference report
    Restricted access - publisher's policy
  • Measuring operating system overhead on CMT processors 

    Radojkovic, Petar; Cakarevic, Vladimir; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Gioiosa, Roberto; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (IEEE Computer Society Publications, 2008)
    Conference report
    Open Access
    Numerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies examine the OS noise for High Performance Computing ...
  • Measuring operating system overhead on Sun UltraSparc T1 processor 

    Radojkovic, Petar; Cakarevic, Vladimir; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Gioiosa, Roberto; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (2009-06)
    Conference report
    Open Access
    Numerous studies have shown that Operating System (OS) noise is one of the reasons for significant performance degradation in clustered architectures. Although many studies examine the OS noise for High Performance Computing, ...
  • Overhead of the spin-lock loop in UltraSPARC T2 

    Cakarevic, Vladimir; Radojkovic, Petar; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Nemirovsky, Mario; Valero Cortés, Mateo; Pajuelo González, Manuel Alejandro; Verdú Mulà, Javier (2008-06-04)
    Conference report
    Open Access
    Spin locks are task synchronization mechanism used to provide mutual exclusion to shared software resources. Spin locks have a good performance in several situations over other synchronization mechanisms, i.e., when on ...
  • Software-controlled priority characterization of POWER5 processor 

    Boneti, Carlos; Cazorla, Francisco; Gioiosa, Roberto; Buyuktosunoglu, Alper; Cher, Chen-Yong; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Conference report
    Open Access
    Due to the limitations of instruction-level parallelism, thread-level parallelism has become a popular way to improve processor performance. One example is the IBM POWER5TM processor, a two-context simultaneous-multithreaded ...
  • Understanding the overhead of the spin-lock loop in CMT architectures 

    Cakarevic, Vladimir; Radojkovic, Petar; Verdú Mulà, Javier; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Pajuelo González, Manuel Alejandro; Nemirovsky, Mario; Valero Cortés, Mateo (2008)
    Conference report
    Open Access
    Spin locks are a synchronization mechanisms used to provide mutual exclusion to shared software resources. Spin locks are used over other synchronization mechanisms in several situations, like when the average waiting ...
  • Understanding the overhead of the spin-lock loop in CMT architectures 

    Cakarevic, Vladimir; Radojkovic, Petar; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Gioiosa, Roberto; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (2008)
    Conference report
    Open Access
    Abstract—Spin locks are a synchronization mechanisms used to provide mutual exclusion to shared software resources. Spin locks are used over other synchronization mechanisms in several situations, like when the average ...