Exploració per autor "Fossati, Luca"
Ara es mostren els items 1-6 de 6
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Contention-aware performance monitoring counter support for real-time MPSoCs
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Comunicació de congrés
Accés obertTasks running in MPSoCs experience contention delays when accessing MPSoC’s shared resources, complicating task timing analysis and deriving execution time bounds. Understanding the Actual Contention Delay (ACD) each task ... -
Data bus slicing for contention-free multicore real-time memory systems
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertMemory access contention is one of the main contributors to tasks' execution time variability in real-Time multicores. Existing techniques to control memory contention based on time-sharing memory access do not scale well ... -
Deconstructing bus access control policies for real-time multicores
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialMulticores may satisfy the growing performance requirements of critical Real-Time systems which has made industry to consider them for future real-time systems. In a multicore, the bus contention-control policy plays a key ... -
Probabilistic timing analysis on time-randomized platforms for the space domain
(Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
Comunicació de congrés
Accés obertTiming Verification is a fundamental step in real-time embedded systems, with measurement-based timing analysis (MBTA) being the most common approach used to that end. We present a Space case study on a real platform that ... -
Seeking time-composable partitions of tasks for COTS multicore processors
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Comunicació de congrés
Accés obertThe timing verification of real-time single core systems involves a timing analysis step that yields an Execution Time Bound (ETB) for each task, followed by a schedulability analysis step, where the scheduling attributes ... -
Validating a timing simulator for the NGMP multicore processor
(European Space Agency (ESA), 2016)
Text en actes de congrés
Accés obertTiming simulation is a key element in multicore systems design. It enables a fast and cost effective design space exploration, allowing to simulate new architectural improvements without requiring RTL abstraction levels. ...
