Now showing items 1-5 of 5

    • An automotive case study on the limits of approximation for object detection 

      Caro Roca, Martí; Tabani, Hamid; Abella Ferrer, Jaume; Moll Echeto, Francisco de Borja; Morancho Llena, Enrique; Canal Corretger, Ramon; Altet Sanahujes, Josep; Calomarde Palomino, Antonio; Cazorla Almeida, Francisco Javier; Rubio Romano, Antonio; Fontova Muste, Pau; Fornt Mas, Jordi (2023-05)
      Article
      Restricted access - publisher's policy
      The accuracy of camera-based object detection (CBOD) built upon deep learning is often evaluated against the real objects in frames only. However, such simplistic evaluation ignores the fact that many unimportant objects ...
    • An energy-efficient GeMM-based convolution accelerator with on-the-fly im2col 

      Fornt Mas, Jordi; Fontova Muste, Pau; Caro Roca, Martí; Abella Ferrer, Jaume; Moll Echeto, Francisco de Borja; Altet Sanahujes, Josep; Studer, Christoph (2023-11)
      Article
      Open Access
      Systolic array architectures have recently emerged as successful accelerators for deep convolutional neural network (CNN) inference. Such architectures can be used to efficiently execute general matrix–matrix multiplications ...
    • Energy efficient object detection for automotive applications with YOLOv3 and approximate hardware 

      Fornt Mas, Jordi; Fontova Muste, Pau; Caro Roca, Martí; Abella Ferrer, Jaume; Moll Echeto, Francisco de Borja; Altet Sanahujes, Josep; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2023)
      Conference report
      Open Access
      Deep neural networks are the dominant models for perception tasks in the automotive domain, but their high computational complexity makes it difficult to execute them in real time with an acceptable power consumption on ...
    • Sargantana: A 1 GHz+ in-order RISC-V processor with SIMD vector extensions in 22nm FD-SOI 

      Soria Pardos, Víctor; Doblas Font, Max; López Paradís, Guillem; Candón Arenas, Gerard; Rodas Quiroga, Narcís; Carril Gil, Xavier; Fontova Muste, Pau; Leyva Santes, Neiel Israel; Marco-Sola, Santiago; Moreto Planas, Miquel (Institute of Electrical and Electronics Engineers (IEEE), 2022)
      Conference report
      Open Access
      The RISC-V open Instruction Set Architecture (ISA) has proven to be a solid alternative to licensed ISAs. In the past 5 years, a plethora of industrial and academic cores and accelerators have been developed implementing ...
    • Sargantana: an academic SoC RISC-V processor in 22nm FDSOI technology 

      Doblas Font, Max; Candón Arenas, Gerard; Carril Gil, Xavier; Dominguez de la Rocha, Marc; Erra, Enric; González Trejo, Alberto; Jiménez, Víctor; Kostalampros, Ioannis-Vatistas; Langarita Benítez, Rubén; Leyva Santes, Neiel; López Paradís, Guillem; Mendoza Escobar, Jonnatan; Oltra Oltra, Josep Angel; Pavón Rivera, Julián; Ramírez Lazo, Cristóbal; Rodas Quiroga, Narcís; Reggiani, Enrico; Rodriguez, Mario; Rojas Morales, Carlos; Ruiz Ramirez, Abraham Josafat; Safadi Figueroa, Hugo Ernesto; Soria Pardos, Víctor; Vargas Valdivieso, Iván; Arreza, Fernando; Figueras Bagué, Roger; Fontova Muste, Pau; Marimon Illana, Joan; Aragonès Cervera, Xavier; Cristal Kestelman, Adrián; Mateo Peña, Diego; Moll Echeto, Francisco de Borja; Moreto Planas, Miquel; Palomar Pérez, Óscar; Sonmez, Nehir; Unsal, Osman Sabri; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2023)
      Conference lecture
      Open Access
      This paper describes the Sargantana System on chip (SoC), a 64-bit RISC-V single core processor designed by a number of academic institutions and manufactured in 22 nm FDSOI technology: BSC, UPC, UB, UAB, CIC-IPN and IMB-CNM ...