Now showing items 1-20 of 134

    • A class of stable nonlinear systems for modelling memory effects in RF power amplifiers 

      Montoro López, Gabriel; Gilabert Pinal, Pere Lluís; Berenguer Sau, Jordi; Bertran Albertí, Eduardo (Escuela Politécnica Superior Ingeniería Gijón, 2006)
      Conference report
      Open Access
    • A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs 

      Salami, Behzad; Unsal, Osman Sabri; Cristal Kestelman, Adrián (IEEE, 2018-12-06)
      Conference lecture
      Open Access
      The power consumption of digital circuits, e.g., Field Programmable Gate Arrays (FPGAs), is directly related to their operating supply voltages. On the other hand, usually, chip vendors introduce a conservative voltage ...
    • A digital memristor emulator for FPGA-based artificial neural networks 

      Vourkas, Ioanis; Abusleme, A.; Ntinas, V.; Sirakoulis, Georgios Ch.; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference report
      Restricted access - publisher's policy
      FPGAs are reconfigurable electronic platforms, well-suited to implement complex artificial neural networks (ANNs). To this end, the compact hardware (HW) implementation of artificial synapses is an important step to obtain ...
    • A generator of numerically-tailored and high-throughput accelerators for batched GEMMs 

      Ledoux Pardo, Luis Eduardo; Casas, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2022)
      Conference report
      Open Access
      We propose a hardware generator of GEMM accelerators. Our generator produces vendor-agnostic HDL describing highly customizable systolic arrays guided by accuracy and energy efficiency goals. The generated arrays have three ...
    • A hardware runtime for task-based programming models 

      Tan, Xubin; Bosch, Jaume; Álvarez, Carlos; Jiménez González, Daniel; Ayguadé Parra, Eduard; Valero Cortés, Mateo (2019-09-01)
      Article
      Open Access
      Task-based programming models such as OpenMP 5.0 and OmpSs are simple to use and powerful enough to exploit task parallelism of applications over multicore, manycore and heterogeneous systems. However, their software-only ...
    • A hardware/software co-design of K-mer counting using a CAPI-enabled FPGA 

      Haghi, Abbas; Álvarez Martí, Lluc; Polo Bardés, Jorda; Diamantopoulos, Dionysios; Hagleitner, Christoph; Moretó Planas, Miquel (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Conference report
      Open Access
      Advances in Next Generation Sequencing (NGS) technologies have caused the proliferation of genomic applications to detect DNA mutations and guide personalized medicine. These applications have an enormous computational ...
    • A hierarchical mathematical model for automatic pipelining and allocation using elastic systems 

      Cortadella, Jordi; Petit Silvestre, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2018)
      Conference report
      Open Access
      The advent of FPGA-based accelerators has encouraged the use of high-level synthesis (HLS) for rapid prototyping and design space exploration. In this context, design optimization at behavioral level becomes a critical ...
    • A method for real-time generation of slew-rate limited envelopes in envelope tracking transmitters 

      Montoro López, Gabriel; Gilabert Pinal, Pere Lluís; Bertran Albertí, Eduardo; Berenguer Sau, Jordi (2010-02)
      Conference report
      Open Access
    • A new switching frequency modulation scheme for EMI reduction in multiconverter topology 

      Mon González, Juan; Gago Barrio, Javier; González Díez, David; Balcells Sendra, Josep; Fernández García, Raúl; Gil Galí, Ignacio (2009)
      Conference report
      Open Access
      This paper presents a modulation scheme in order to reduce conducted Electromagnetic Interference (EMI) generated by modular power converters with parallel topology. The proposed scheme is based on a combination of ...
    • A novel FPGA-based high throughput accelerator for binary search trees 

      Melikoglu, Oyku; Ergin, Oguz; Salami, Behzad; Pavón Rivera, Julián; Unsal, Osman Sabri; Cristal Kestelman, Adrián (Institute of Electrical and Electronics Engineers (IEEE), 2019)
      Conference report
      Open Access
      This paper presents a deeply pipelined and massively parallel Binary Search Tree (BST) accelerator for Field Programmable Gate Arrays (FPGAs). Our design relies on the extremely parallel on-chip memory, or Block RAMs (BRAMs) ...
    • A scalable bandwidth and frequency-dependent DPD linearizer for user equipment power amplifiers with nonflat frequency response 

      Li, Wantao; Guo, Yan; Montoro López, Gabriel; Gilabert Pinal, Pere Lluís (Institute of Electrical and Electronics Engineers (IEEE), 2023-10-24)
      Article
      Open Access
      This article presents a scalable digital predistortion (DPD) linearizer for handset power amplifiers (PAs) with nonflat frequency response and assuming a 5G scenario with dynamic resource blocks (RBs) reallocation. The ...
    • A template system for the efficient compilation of domain abstractions onto reconfigurable computers 

      Shafiq, Muhammad; Pericàs Gleim, Miquel; Ayguadé Parra, Eduard (2011)
      Conference report
      Restricted access - publisher's policy
      Past research has addressed the issue of using FPGAs as accelerators for HPC systems. However, writing low level code for an efficient, portable and scalable architecture altogether has been always a ...
    • Abisko: Deep codesign of an architecture for spiking neural networks using novel neuromorphic materials 

      Vetter, Jeffrey; Date, Prasanna; Fahim, Farah; Kulkarni, Shruti R.; Maksymovych, Petro; Talin, Alec; González Tallada, Marc; Vanna Iampikul, Pruek; Young, Aaron Reed; Brooks, David (SAGE publishing, 2023-07)
      Article
      Open Access
      The Abisko project aims to develop an energy-efficient spiking neural network (SNN) computing architecture and software system capable of autonomous learning and operation. The SNN architecture explores novel neuromorphic ...
    • Acceleració d'una aplicació de detecció facial mitjançant FPGA 

      Mateu Sebastián, Marc (Universitat Politècnica de Catalunya, 2017)
      Bachelor thesis
      Open Access
      Actualment, les aplicacions que basen el seu funcionament en el processament d'imatges requereixen d'un gran nivell de còmput. Tot i que al llarg del temps s'han desenvolupat diversos algoritmes per intentar ...
    • Acceleration of Complex Algorithms on a Fast Reconfigurable Embedded System on Spartan-3 

      Canto Navarro, Enrique Fernando; Fons, Mariano; López García, Mariano; Ramos Lara, Rafael Ramón (2009)
      Conference report
      Open Access
      Complex algorithms usually require several computation stages. Many embedded microprocessors have not enough computational performance to resolve these algorithms in a reasonable time, so dedicated coprocessors accelerate ...
    • Advanced pattern based memory controller for FPGA based HPC applications 

      Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Conference report
      Restricted access - publisher's policy
      The ever-increasing complexity of high-performance computing applications limits performance due to memory constraints in FPGAs. To address this issue, we propose the Advanced Pattern based Memory Controller (APMC), which ...
    • AIG transformations to improve LUT mapping for FPGAs 

      Barrachina Hernandez, Pol (Universitat Politècnica de Catalunya, 2022-06-28)
      Master thesis
      Open Access
      A Field-Programmable Gate Array (FPGA) is a general re-configurable device for implementing logic circuits. This technology is extensively used for prototyping circuits due to its cost and speed. The underlying implementation ...
    • AMC: Advanced Multi-accelerator Controller 

      Hussain, Tassadaq; Haider, Amna; Gursal, Shakaib A.; Ayguadé Parra, Eduard (2015-01)
      Article
      Open Access
      The rapid advancement, use of diverse architectural features and introduction of High Level Synthesis (HLS) tools in FPGA technology have enhanced the capacity of data-level parallelism on a chip. A generic FPGA based HLS ...
    • AMMC: advance multi-core memory controller 

      Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Conference lecture
      Open Access
      In this work, we propose an efficient scheduler and intelligent memory manager known as AMMC (Advanced Multi-Core Memory Controller), which proficiently handles data movement and computational tasks. The proposed AMMC ...
    • An academic RISC-V silicon implementation based on open-source components 

      Abella Ferrer, Jaume; Bulla, Calvin; Cabo Pitarch, Guillem; Cazorla Almeida, Francisco Javier; Cristal Kestelman, Adrián; Doblas Font, Max; Figueras Bagué, Roger; González Trejo, Alberto; Hernández Luz, Carles; Hernández Calderón, César Alejandro; Jiménez Arador, Víctor; Kosmidis, Leonidas; Kostalampros, Ioannis-Vatistas; Langarita Benítez, Rubén; Leyva Santes, Neiel; López Paradís, Guillem; Marimon Illana, Joan; Martínez Martínez, Ricardo; Mendoza Escobar, Jonnatan; Moll Echeto, Francisco de Borja; Moretó Planas, Miquel; Pavón Rivera, Julián; Ramírez Lazo, Cristóbal; Ramírez Salinas, Marco Antonio; Rojas Morales, Carlos; Rubio Sola, Jose Antonio; Ruiz, Abraham Josafat; Sonmez, Nehir; Soria Pardos, Víctor; Teres Teres, Lluis; Unsal, Osman Sabri; Valero Cortés, Mateo; Vargas Valdivieso, Iván; Villa Vargas, Luis Alfonso (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Conference report
      Open Access
      The design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V ...