Now showing items 1-20 of 76

  • Acceleració d'una aplicació de detecció facial mitjançant FPGA 

    Mateu Sebastián, Marc (Universitat Politècnica de Catalunya, 2017)
    Bachelor thesis
    Open Access
    Actualment, les aplicacions que basen el seu funcionament en el processament d'imatges requereixen d'un gran nivell de còmput. Tot i que al llarg del temps s'han desenvolupat diversos algoritmes per intentar ...
  • Acceleration of Complex Algorithms on a Fast Reconfigurable Embedded System on Spartan-3 

    Canto Navarro, Enrique Fernando; Fons, Mariano; López García, Mariano; Ramos Lara, Rafael Ramón (2009)
    Conference report
    Open Access
    Complex algorithms usually require several computation stages. Many embedded microprocessors have not enough computational performance to resolve these algorithms in a reasonable time, so dedicated coprocessors accelerate ...
  • A class of stable nonlinear systems for modelling memory effects in RF power amplifiers 

    Montoro López, Gabriel; Gilabert Pinal, Pere Lluís; Berenguer Sau, Jordi; Bertran Albertí, Eduardo (Escuela Politécnica Superior Ingeniería Gijón, 2006)
    Conference report
    Open Access
  • A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs 

    Salami, Behzad; Unsal, Osman; Cristal Kestelman, Adrián (IEEE, 2018-12-06)
    Conference lecture
    Open Access
    The power consumption of digital circuits, e.g., Field Programmable Gate Arrays (FPGAs), is directly related to their operating supply voltages. On the other hand, usually, chip vendors introduce a conservative voltage ...
  • A digital memristor emulator for FPGA-based artificial neural networks 

    Vourkas, Ioanis; Abusleme, A.; Ntinas, V.; Sirakoulis, Georgios Ch.; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Restricted access - publisher's policy
    FPGAs are reconfigurable electronic platforms, well-suited to implement complex artificial neural networks (ANNs). To this end, the compact hardware (HW) implementation of artificial synapses is an important step to obtain ...
  • Advanced pattern based memory controller for FPGA based HPC applications 

    Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
    Restricted access - publisher's policy
    The ever-increasing complexity of high-performance computing applications limits performance due to memory constraints in FPGAs. To address this issue, we propose the Advanced Pattern based Memory Controller (APMC), which ...
  • A hierarchical mathematical model for automatic pipelining and allocation using elastic systems 

    Cortadella, Jordi; Petit Silvestre, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Conference report
    Open Access
    The advent of FPGA-based accelerators has encouraged the use of high-level synthesis (HLS) for rapid prototyping and design space exploration. In this context, design optimization at behavioral level becomes a critical ...
  • AMC: Advanced Multi-accelerator Controller 

    Hussain, Tassadaq; Haider, Amna; Gursal, Shakaib A.; Ayguadé Parra, Eduard (2015-01)
    Article
    Open Access
    The rapid advancement, use of diverse architectural features and introduction of High Level Synthesis (HLS) tools in FPGA technology have enhanced the capacity of data-level parallelism on a chip. A generic FPGA based HLS ...
  • A method for real-time generation of slew-rate limited envelopes in envelope tracking transmitters 

    Montoro López, Gabriel; Gilabert Pinal, Pere Lluís; Bertran Albertí, Eduardo; Berenguer Sau, Jordi (2010-02)
    Conference report
    Open Access
  • AMMC: advance multi-core memory controller 

    Hussain, Tassadaq; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference lecture
    Open Access
    In this work, we propose an efficient scheduler and intelligent memory manager known as AMMC (Advanced Multi-Core Memory Controller), which proficiently handles data movement and computational tasks. The proposed AMMC ...
  • Anàlisi de la interconnexió de dispositius lògics programables mitjançant Ethernet 

    Peshevski, Marko (Universitat Politècnica de Catalunya, 2017-02-09)
    Master thesis
    Restricted access - author's decision
    En aquest treball s'estudia com fer funcionar Ethernet des d'una placa amb FPGA (de l'anglès Field Programmable Gate Array). Aquests són dispositius electrònics que permeten reprogramar la lògica que contenen dins per ...
  • A new switching frequency modulation scheme for EMI reduction in multiconverter topology 

    Mon González, Juan; Gago Barrio, Javier; González Díez, David; Balcells Sendra, Josep; Fernández García, Raúl; Gil Galí, Ignacio (2009)
    Conference report
    Open Access
    This paper presents a modulation scheme in order to reduce conducted Electromagnetic Interference (EMI) generated by modular power converters with parallel topology. The proposed scheme is based on a combination of ...
  • Aplicación de técnicas avanzadas de lienalización a sistemas de RF/microondas 

    García, J.A.; Bertran Albertí, Eduardo; Begrains, J.; Montoro López, Gabriel; Ares, F.; Cabria, L. (Editorial de la UPV, 2005)
    Conference report
    Open Access
  • Aplicaciones didácticas de PLD/FPGA para las asignaturas de sistemas digitales 

    González Rodríguez, Jonatan (Universitat Politècnica de Catalunya, 2012-03-07)
    Bachelor thesis
    Open Access
    Este proyecto es una guía destinada a los futuros alumnos de la asignatura CSD que se imparte en el grado en Ingeniería de Sistemas de Telecomunicaciones en la EETAC y para personas que se inicien en el lenguaje de ...
  • Application Acceleration on FPGAs with OmpSs@FPGA 

    Bosch, Jaume; Tan, Xubin; Filgueras Izquierdo, Antonio; Vidal, Miquel; Mateu, Marc; Jiménez-González, Daniel; Álvarez, Carlos; Martorell Bofill, Xavier; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José (Institute of Electrical and Electronics Engineers (IEEE), 2019)
    Conference report
    Open Access
    OmpSs@FPGA is the flavor of OmpSs that allows offloading application functionality to FPGAs. Similarly to OpenMP, it is based on compiler directives. While the OpenMP specification also includes support for heterogeneous ...
  • A template system for the efficient compilation of domain abstractions onto reconfigurable computers 

    Shafiq, Muhammad; Pericàs Gleim, Miquel; Ayguadé Parra, Eduard (2011)
    Conference report
    Restricted access - publisher's policy
    Past research has addressed the issue of using FPGAs as accelerators for HPC systems. However, writing low level code for an efficient, portable and scalable architecture altogether has been always a ...
  • AXIOM: a hardware-software platform for cyber physical systems 

    Mazumdar, Somnath; Ayguadé Parra, Eduard; Bettin, Nicola; Bueno Hedo, Javier; Ermini, Sara; Filgueras Izquierdo, Antonio; Jiménez González, Daniel; Álvarez Martínez, Carlos; Martorell Bofill, Xavier; Montefoschi, Francesco; Oro Garcia, David; Pnevmatikatos, Dionisis; Rizzo, Antonio; Theodoropoulos, Dimitris; Giorgi, Roberto (2016)
    Conference report
    Restricted access - publisher's policy
    Cyber-Physical Systems (CPSs) are widely necessary for many applications that require interactions with the humans and the physical environment. A CPS integrates a set of hardware-software components to distribute, execute ...
  • Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-Chip Memories 

    Salami, Behzad; Unsal, Osman S.; Cristal Kestelman, Adrián (IEEE, 2018-12-13)
    Conference lecture
    Open Access
    In this work, we evaluate aggressive undervolting, i.e., voltage scaling below the nominal level to reduce the energy consumption of Field Programmable Gate Arrays (FPGAs). Usually, voltage guardbands are added by chip ...
  • Considerations in using OpenCL on GPUs and FPGAs for throughput-oriented genomics workloads 

    Cadenelli, Nicola; Jaksic, Zoran; Polo Bardés, Jorda; Carrera Pérez, David (Elsevier, 2019-05)
    Article
    Open Access
    The recent upsurge in the available amount of health data and the advances in next-generation sequencing are setting the ground for the long-awaited precision medicine. To process this deluge of data, bioinformatics workloads ...
  • Contribution to conducted EMI reduction in multiconverter topology 

    Mon González, Juan; González Díez, David; Gago Barrio, Javier; Balcells Sendra, Josep; Fernández García, Raúl; Gil Galí, Ignacio (2009-11)
    Conference report
    Open Access
    This paper contributes to the conducted EMI reduction generated by switched power converters operating in multiconverter arrangement. The EMI reduction is achieved by means of the combination of two techniques: interleaving ...