Now showing items 1-10 of 10

    • Analysis of the Task Superscalar architecture hardware design 

      Yazdanpanah Ahmadabadi, Fahimeh; Jiménez González, Daniel; Álvarez Martínez, Carlos; Etsion, Yoav; Badia Sala, Rosa Maria (Springer, 2013)
      Conference report
      Open Access
      In this paper, we analyze the operational flow of two hardware implementations of the Task Superscalar architecture. The Task Superscalar is an experimental task based dataflow scheduler that dynamically detects inter-task ...
    • CODOMs: Protecting software with code-centric memory domains 

      Vilanova, Lluís; Ben-Yehuda, Muli; Navarro, Nacho; Etsion, Yoav; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Conference report
      Restricted access - publisher's policy
      Today's complex software systems are neither secure nor reliable. The rudimentary software protection primitives provided by current hardware forces systems to run many distrusting software components (e.g., procedures, ...
    • Direct Inter-Process Communication (dIPC): Repurposing the CODOMs architecture to accelerate IPC 

      Vilanova, Lluis; Jordà Peroliu, Marc; Navarro, Nacho; Etsion, Yoav; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2017)
      Conference report
      Open Access
      In current architectures, page tables are the fundamental mechanism that allows contemporary OSs to isolate user processes, binding each thread to a specific page table. A thread cannot therefore directly call another ...
    • Interleaving granularity on high bandwidth memory architecture for CMPs 

      Cabarcas, Felipe; Rico Carro, Alejandro; Etsion, Yoav; Ramírez Bellido, Alejandro (IEEE Computer Society Publications, 2010)
      Conference report
      Open Access
      Memory bandwidth has always been a critical factor for the performance of many data intensive applications. The increasing processor performance, and the advert of single chip multiprocessors have increased the memory ...
    • Introducing speculative optimizations in task dataflow with language extensions and runtime support 

      Azuelos, Nathaniel; Etsion, Yoav; Keidar, Idit; Zaks, A.; Ayguadé Parra, Eduard (2012)
      Conference report
      Open Access
      We argue that speculation leads to increased parallelism in the coarse-grain dataflow paradigm. To do so, we present a framework for adding speculation in a popular and well-established framework. We specify a limited ...
    • LEGaTO: first steps towards energy-efficient toolset for heterogeneous computing 

      Cristal, Adrian; Unsal, Osman S.; Martorell, Xavier; Carpenter, Paul; de la Cruz, Raul; Bautista, Leonardo; Jimenez, Daniel; Alvarez, Carlos; Salami, Behzad; Madonar, Sergi; Pericàs, Miquel; Trancoso, Pedro; vor dem Berge, Micha; Billung-Meyer, Gunnar; Krupop, Stefan; Christmann, Wolfgang; Klawonn, Frank; Mihklafi, Amani; Becker, Tobias; Gaydadjiev, Georgi; Salomonsson, Hans; Dubhashi, Devdatt; Port, Oron; Hadar, Elad; Etsion, Yoav; Fetzer, Christof; Hagemeyer, Jens; Jungeblut, Thorsten; Kucza, Nils; Kaiser, Martin; Porrmann, Mario; Pasin, Marcelo; Schiavoni, Valerio; Rocha, Isabelly; Göttel, Christian; Felber, Pascal (ACM, 2018-07-15)
      Conference lecture
      Open Access
      LEGaTO is a three-year EU H2020 project which started in December 2017. The LEGaTO project will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of ...
    • LEGaTO: towards energy-efficient, secure, fault-tolerant toolset for heterogeneous computing 

      Cristal Kestelman, Adrián; Unsal, Osman S.; Martorell, Xavier; Carpenter, Paul; de la Cruz, Raul; Bautista, Leonardo; Jimenez, Daniel; Alvarez, Carlos; Salami, Behzad; Madonar, Sergi; Pericàs, Miquel; Trancoso, Pedro; von dem Berge, Micha; Billung-Meyer, Gunnar; Krupop, Stefan; Christmann, Wolfgang; Klawonn, Frank; Mihklafi, Amani; Becker, Tobias; Gaydadjiev, Georgi; Salomonsson, Hans; Dubhashi, Devdatt; Port, Oron; Etsion, Yoav; Nowack, Vesna; Fetzer, Christof; Hagemeyer, Jens; Jungeblut, Thorsten; Kucza, Nils; Kaiser, Martin; Porrmann, Mario; Pasin, Marcelo; Schiavoni, Valerio; Rocha, Isabelly; Göttel, Christian; Felber, Pascal (Association for Computing Machinery (ACM), 2018-05-08)
      Conference lecture
      Open Access
      LEGaTO is a three-year EU H2020 project which started in December 2017. The LEGaTO project will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of ...
    • On the simulation of large-scale architectures using multiple application abstraction levels 

      Rico Carro, Alejandro; Cabarcas, Felipe; Villavieja Prados, Carlos; Pavlovic, Milan; Vega, Augusto; Etsion, Yoav; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2012-01-23)
      Article
      Restricted access - publisher's policy
      Simulation is a key tool for computer architecture research. In particular, cycle-accurate simulators are extremely important for microarchitecture exploration and detailed design decisions, but they are slow and, so, not ...
    • Task superscalar: an out-of-order task pipeline 

      Etsion, Yoav; Cabarcas, Felipe; Rico Carro, Alejandro; Ramírez Bellido, Alejandro; Badia Sala, Rosa Maria; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (IEEE Computer Society Publications, 2010)
      Conference report
      Open Access
      We present Task Superscalar, an abstraction of instruction-level out-of-order pipeline that operates at the tasklevel. Like ILP pipelines, which uncover parallelism in a sequential instruction stream, task superscalar ...
    • Trace-driven simulation of multithreaded applications 

      Rico Carro, Alejandro; Duran González, Alejandro; Cabarcas, Felipe; Etsion, Yoav; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2011)
      Conference report
      Restricted access - publisher's policy
      Over the past few years, computer architecture research has moved towards execution-driven simulation, due to the inability of traces to capture timing-dependent thread execution interleaving. However, trace-driven simulation ...