Now showing items 1-3 of 3

    • Analysis and simulation of data prefetching algorithms for last-level cache memory 

      Escuín Blasco, Carlos (Universitat Politècnica de Catalunya, 2018-06-25)
      Master thesis
      Open Access
      Covenantee:   České vysoké učení technické v Praze
      Analysis and simulation of data prefetching algorithms for last-level cache memory. Analysis and comparison of one of the latest data prefetching algorithms in terms of performance, network utilization and prefetching accuracy.
    • Pronóstico de capacidad efectiva y prestaciones en una cache no volátil de último nivel 

      Escuín Blasco, Carlos; Monreal Arnal, Teresa; Llaberia Griñó, José M.; Ibáñez Marín, Pablo Enrique; Viñals Yúfera, Victor (Sociedad de Arquitectura y Tecnología de Computadores (SARTECO), 2021)
      Conference report
      Open Access
      La degradación debida a las escrituras que sufren las bitcells implementadas con tecnologi´as de memoria no volátil (NVM) es uno de los principales escollos que se presentan a la hora de construir la cache de último nivel ...
    • STT-RAM memory hierarchy designs aimed to performance, reliability and energy consumption 

      Escuín Blasco, Carlos; Monreal Arnal, Teresa; Llaberia Griñó, José M.; Viñals Yúfera, Victor; Ibáñez Marín, Pablo (European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), 2019)
      Conference lecture
      Open Access
      Current applications demand larger on-chip memory capacity since off-chip memory accesses be-come a bottleneck. However, if we want to achieve this by scaling down the transistor size of SRAM-based Last-Level Caches (LLCs) ...