Now showing items 1-7 of 7

    • Analysis and simulation of data prefetching algorithms for last-level cache memory 

      Escuín Blasco, Carlos (Universitat Politècnica de Catalunya, 2018-06-25)
      Master thesis
      Open Access
      Covenantee:   České vysoké učení technické v Praze
      Analysis and simulation of data prefetching algorithms for last-level cache memory. Analysis and comparison of one of the latest data prefetching algorithms in terms of performance, network utilization and prefetching accuracy.
    • Compression-aware and performance-efficient insertion policies for long-lasting hybrid LLCs 

      Escuín Blasco, Carlos; Ali Khan, Asif; Ibáñez, Pablo Enrique; Monreal Arnal, Teresa; Castrillón, Jerónimo; Viñals Yúfera, Victor (Institute of Electrical and Electronics Engineers (IEEE), 2023)
      Conference report
      Open Access
      Emerging non-volatile memory (NVM) technologies can potentially replace large SRAM memories such as the last-level cache (LLC). However, despite recent advances, NVMs suffer from higher write latency and limited write ...
    • HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches 

      Escuín Blasco, Carlos; Ali Khan, Asif; Ibáñez Marín, Pablo Enrique; Monreal Arnal, Teresa; Viñals Yúfera, Victor; Castrillón, Jerónimo (Association for Computing Machinery (ACM), 2022)
      Conference report
      Restricted access - publisher's policy
      Recent years have seen a rising trend in the exploration of non-volatile memory (NVM) technologies in the memory subsystem. Particularly in the cache hierarchy, hybrid last-level cache (LLC) solutions are proposed to meet ...
    • L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime 

      Escuín Blasco, Carlos; Ibáñez Marín, Pablo; Navarro, Denis; Monreal Arnal, Teresa; Llaberia Griñó, José M.; Viñals Yúfera, Victor (Public Library of Science (PLOS), 2023-02-07)
      Article
      Open Access
      Several emerging non-volatile (NV) memory technologies are rising as interesting alternatives to build the Last-Level Cache (LLC). Their advantages, compared to SRAM memory, are higher density and lower static power, but ...
    • Leveraging data compression for performance-efficient and long-lasting NVM-based last-level cache 

      Escuín Blasco, Carlos; Ali Khan, Asif; Ibáñez Marín, Pablo Enrique; Monreal Arnal, Teresa; Navarro, Denis; Llaberia Griñó, José M.; Castrillón, Jerónimo; Viñals Yúfera, Victor (University of California, Los Angeles (UCLA), 2023)
      Conference lecture
      Open Access
      Non-volatile memory (NVM) technologies are interesting alternatives for building on-chip Last-Level Caches (LLCs). Their advantages, compared to SRAM memory, are higher density and lower static power, but each write operation ...
    • Pronóstico de capacidad efectiva y prestaciones en una cache no volátil de último nivel 

      Escuín Blasco, Carlos; Monreal Arnal, Teresa; Llaberia Griñó, José M.; Ibáñez Marín, Pablo Enrique; Viñals Yúfera, Victor (Sociedad de Arquitectura y Tecnología de Computadores (SARTECO), 2021)
      Conference report
      Open Access
      La degradación debida a las escrituras que sufren las bitcells implementadas con tecnologi´as de memoria no volátil (NVM) es uno de los principales escollos que se presentan a la hora de construir la cache de último nivel ...
    • STT-RAM memory hierarchy designs aimed to performance, reliability and energy consumption 

      Escuín Blasco, Carlos; Monreal Arnal, Teresa; Llaberia Griñó, José M.; Viñals Yúfera, Victor; Ibáñez Marín, Pablo (European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), 2019)
      Conference lecture
      Open Access
      Current applications demand larger on-chip memory capacity since off-chip memory accesses be-come a bottleneck. However, if we want to achieve this by scaling down the transistor size of SRAM-based Last-Level Caches (LLCs) ...