Now showing items 1-3 of 3

  • ReD: A policy based on reuse detection for demanding block selection in last-level Caches 

    Díaz Maag, Javier; Ibáñez Marín, Pablo Enrique; Monreal Arnal, Teresa; Viñals Yúfera, Víctor; Llaberia Griñó, José M. (2017)
    Conference report
    Open Access
    In this paper, we propose a new block selection policy for Last-Level Caches (LLCs) that decides, based on Reuse Detection, whether a block coming from main memory is inserted, or not, in the LLC. The proposed policy, ...
  • Reuse Detector: improving the management of STT-RAM SLLCs 

    Rodríguez Rodríguez, Roberto; Díaz Maag, Javier; Castro, Fernando; Ibáñez Marín, Pablo Enrique; Chaver Martínez, Daniel A.; Viñals Yúfera, Víctor; Sáez Alcaide, Juan Carlos; Prieto Matías, Manuel; Piñuel, Luis; Monreal Arnal, Teresa; Llaberia Griñó, José M. (2018-06-01)
    Article
    Open Access
    Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-Transfer Torque RAM (STT-RAM) is currently ...
  • Selección de contenidos basada en reuso para caches compartidas en exclusión 

    Díaz Maag, Javier; Monreal Arnal, Teresa; Viñals Yúfera, Víctor; Ibáñez Marín, Pablo Enrique; Llaberia Griño, José María (2015)
    Conference report
    Open Access
    Publicaciones previas revelan que el flujo de referencias que llega a la cache compartida (SLLC) de un chip multiprocesador muestra poca localidad temporal. Sin embargo, muestra localidad de reuso, es decir, los bloques ...