Now showing items 1-20 of 45

  • An approximate analysis of synchronous multiple bus 

    González Peña, Luis Eduardo; Sanvicente Gargallo, Emilio (1985)
    External research report
    Open Access
    This paper presents an approximate analytic model for evaluating the performance of a loosely coupled multiprocessor architecture whose memory, organized in modules, is shared by all the processors. Each memory module (Mi) ...
  • An hybrid eDRAM/SRAM macrocell to implement first-level data caches 

    Valero, Alejandro; Sahuquillo, Julio; Petit, Salvador; Lorente, Vicente; Canal Corretger, Ramon; López, Pedro; Duato, José (Association for Computing Machinery (ACM), 2009)
    Conference report
    Restricted access - publisher's policy
    SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are ...
  • Another trip to the wall: how much will stacked DRAM benefit HPC? 

    Radulovic, Milan; Zivanovic, Darko; Ruiz, Daniel; De Supinski, Bronis; McKee, Sally; Radojkovic, Petar; Ayguadé Parra, Eduard (Association for Computing Machinery (ACM), 2015)
    Conference report
    Restricted access - publisher's policy
    First defined two decades ago, the memory wall remains a fundamental limitation to system performance. Recent innovations in 3D-stacking technology enable DRAM devices with much higher bandwidths than traditional DIMMs. ...
  • A view of the future of memory technologies and systems 

    Pawlowski, J. Thomas (Barcelona Supercomputing Center, 2019)
    Other
    Open Access
  • Compartición de espacio entre instrucciones 

    Rodríguez Lafuente, Clemente; Viñals Yúfera, Víctor; Labarta, Jesús (E.T.S.I. de Telecomunicación, 1985)
    Conference report
    Open Access
    Un gran número de computadores en la actualidad usan memoria cache para adaptar la velocidad de la memoria a la del procesador, o bien reducir el tráfico en sistemas multiprocesadores. En la actualidad un tema discutido ...
  • Conflict-free strides for vectors in matched memories 

    Valero Cortés, Mateo; Lang, Tomas; Llaberia Griñó, José M.; Peiron Guàrdia, Montse; Navarro Guerrero, Juan José; Ayguadé Parra, Eduard (1991-12)
    Article
    Open Access
    Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free access to one family of strides in vector processors with matched memories. The paper extends these ...
  • Cost-effective compiler directed memory prefetching and bypassing 

    Ortega Fernández, Daniel; Ayguadé Parra, Eduard; Baer, Jean-Loup; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2002)
    Conference report
    Open Access
    Ever increasing memory latencies and deeper pipelines push memory farther from the processor. Prefetching techniques aim is to bridge these two gaps by fetching data in advance to both the L1 cache and the register file. ...
  • CRAID: Online RAID upgrades using dynamic hot data reorganization 

    Miranda Bueno, Alberto; Cortés, Toni (USENIX Association, 2014)
    Conference report
    Open Access
    Current algorithms used to upgrade RAID arrays typically require large amounts of data to be migrated, even those that move only the minimum amount of data required to keep a balanced data load. This paper presents CRAID, ...
  • Defending cache memory against cold-boot attacks boosted by power or EM radiation analysis 

    Neagu, Madalin; Manich Bou, Salvador (2017-04)
    Article
    Open Access
    Some algorithms running with compromised data select cache memory as a type of secure memory where data is confined and not transferred to main memory. However, cold-boot attacks that target cache memories exploit the data ...
  • Designing endurable phase-change memories:balancing bit flips and exploiting multi-level storage capability 

    Sarbazi-Azad, Hamid (Barcelona Supercomputing Center, 2019)
    Other
    Open Access
  • Distributing orthogonal redundancy on adaptive disk arrays 

    González, José Luis; Cortés, Toni (Springer, 2008)
    Conference report
    Restricted access - publisher's policy
    When upgrading storage systems, the key is migrating data from old storage subsystems to the new ones for achieving a data layout able to deliver high performance I/O, increased capacity and strong data availability while ...
  • ECHOFS: a scheduler-guided temporary filesystem to leverage node-local NVMS 

    Miranda, Alberto; Nou Castell, Ramon; Cortés, Toni (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Conference report
    Open Access
    The growth in data-intensive scientific applications poses strong demands on the HPC storage subsystem, as data needs to be copied from compute nodes to I/O nodes and vice versa for jobs to run. The emerging trend of adding ...
  • Enabling a reliable STT-MRAM main memory simulation 

    Asifuzzaman, Kazi; Sánchez Verdejo, Rommel; Radojković, Petar (Barcelona Supercomputing Center, 2018-04-24)
    Conference report
    Open Access
  • Freezing Time: a new approach for emulating fast storage devices using VM 

    Bona, Luis C.E.; Elias, Alessandro; Ziviani, Andre P.; Cortés, Toni; Nou Castell, Ramon; Alves, Marco A.Z. (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Conference report
    Open Access
    Recently we are seeing a considerable effort from both academy and industry in proposing new technologies for storage devices. Often these devices are not readily available for evaluation and methods to allow performing ...
  • HetFS: A heterogeneous file system for everyone 

    Koloventzos, Georgios; Nou Castell, Ramon; Miranda, Alberto; Cortés, Toni (Springer, 2017)
    Conference report
    Open Access
    Storage devices have been getting more and more diverse during the last decade. The advent of SSDs made it painfully clear that rotating devices, such as HDDs or magnetic tapes, were lacking in regards to response time. ...
  • High quality, scalable and parallel community detection for large real graphs 

    Prat Pérez, Arnau; Domínguez Sal, David; Larriba Pey, Josep (Association for Computing Machinery (ACM), 2014)
    Conference report
    Restricted access - publisher's policy
    Community detection has arisen as one of the most relevant topics in the field of graph mining, principally for its applications in domains such as social or biological networks analysis. Different community detection ...
  • Implementació en HDL d'un arbre binari de cerca auto-balancejat 

    Mercadé Ibáñez, Àlvar (Universitat Politècnica de Catalunya, 2017-06-27)
    Master thesis (pre-Bologna period)
    Open Access
    Covenantee:  Barcelona Supercomputing Centre
    Amb la proliferació de les arquitectures multi-core i many-core, s’han emprat molts esforços en l’especificació i la implementació de nous models de programació, que facilitessin als desenvolupadors de programari la ...
  • Increasing the number of strides for conflict-free vector access 

    Valero Cortés, Mateo; Lang, Tomas; Llaberia Griñó, José M.; Peiron Guàrdia, Montse; Ayguadé Parra, Eduard; Navarro Guerrero, Juan José (1992-05)
    Article
    Open Access
    Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free vector access for some strides in vector processors with multi-module memories. In this paper, we ...
  • ITCA: Inter-Task Conflict-Aware CPU accounting for CMP 

    Luque, Carlos; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Valero Cortés, Mateo (2010)
    Conference report
    Open Access
    Chip-MultiProcessors (CMP) introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is ...
  • Last Bank: dealing with address reuse in non-uniform cache architecture for CMPs 

    Lira Rueda, Javier; Molina Clemente, Carlos; González Colás, Antonio María (2009-01-16)
    External research report
    Open Access
    In response to the constant increase in wire delays, Non-Uniform Cache Architecture (NUCA) has been introduced as an effective memory model for dealing with growing memory latencies. This architecture divides a large memory ...