Ara es mostren els items 1-20 de 167

  • A decoupled KILO-instruction processor 

    Pericàs Gleim, Miquel; Cristal Kestelman, Adrián; González García, Rubén; Jiménez, Daniel A.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2006)
    Text en actes de congrés
    Accés obert
    Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elusive goal. Traditional processors are ...
  • A fast and efficient algorithm to identify clusters in networks 

    Comellas Padró, Francesc de Paula; Miralles de la Asunción, Alicia (2010-11-01)
    Article
    Accés restringit per política de l'editorial
    A characteristic feature of many relevant real life networks, like the WWW, Internet, transportation and communication networks, or even biological and social networks, is their clustering structure. We discuss in this ...
  • A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness 

    Cook, Henry; Moreto Planas, Miquel; Bird, Sarah L.; Dao, Khanh; Patterson, David; Asanovic, Krste (ACM, 2013)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Computing workloads often contain a mix of interactive, latency-sensitive foreground applications and recurring background computations. To guarantee responsiveness, interactive and batch applications are often run on ...
  • A hybrid web server architecture for secure e-business web applications 

    Beltran Querol, Vicenç; Carrera Pérez, David; Guitart Fernández, Jordi; Torres Viñals, Jordi; Ayguadé Parra, Eduard (2005-09)
    Article
    Accés restringit per política de l'editorial
    Nowadays the success of many e-commerce applications, such as on-line banking, depends on their reliability, robustness and security. Designing a web server architecture that keeps these properties under high loads is a ...
  • A Rudimentary Machine. Experiences in the Design of a Pedagogic Computer 

    Pastor Llorens, Enric; Sánchez Carracedo, Fermín; Corral González, Anna M. del (Publicat en web, 1999-07)
    Article
    Accés obert
    This paper describes a pedagogic computer named \M aquina Rudimentaria". This computer has been de- signed to be used in a rst course on logic design or com- puter architecture; orthogonality and simplicity have been the ...
  • A self-adaptive hardware architecture with fault tolerance capabilities 

    Soto, Javier; Moreno Aróstegui, Juan Manuel; Cabestany Moncusí, Joan (2013-12-09)
    Article
    Accés restringit per política de l'editorial
    This paper describes a Fault Tolerance System (FTS) implemented in a new self-adaptive hardware architecture. This architecture is based on an array of cells that implements in a distributed way self-adaptive capabilities. ...
  • A software-hardware hybrid steering mechanism for clustered microarchitectures 

    Cai, Qiong; Codina Viñas, Josep M; González González, José; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Text en actes de congrés
    Accés obert
    Clustered microarchitectures provide a promising paradigm to solve or alleviate the problems of increasing microprocessor complexity and wire delays. High- performance out-of-order processors rely on hardware-only steering ...
  • A systolic algorithm for the fast computation of the connected components of a graph 

    Núñez, Fernando J.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1988)
    Text en actes de congrés
    Accés obert
    The authors consider the description of a systolic algorithm to solve the connected-component problem. It is executed in a ring topology with N processors, requiring O(Nlog N) time without regard to the graph's sparsity. ...
  • A two-dimensional architecture for end-to-end resource management in virtual network environments 

    Wang, Ning; Zhang, Yi; Serrat Fernández, Juan; Gorricho Moreno, Juan Luis; Guo, Tao; Hu, Zheng; Zhang, Ping (2012-09)
    Article
    Accés restringit per política de l'editorial
    In recent years, various network virtualization techniques have been proposed for flexibly supporting heterogeneous services over virtual network platforms. However, systematic views on how virtual network resources (VNRs) ...
  • Adaptación a un entorno J2EE desde un sistema centralizado Host 

    Ferré Vaquer, Maria Teresa (Universitat Politècnica de Catalunya, 2013-12-20)
    Projecte/Treball Final de Carrera
    Accés restringit per decisió de l'autor
    Explain J2EE adaptation process, advantages, functional design, etc.
  • Adaptive fault-tolerant architecture for unreliable device technologies 

    Aymerich, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio (CRC Press, Taylor and Francis Group, 2013-06-03)
    Capítol de llibre
    Accés restringit per política de l'editorial
    Nanoelectronic Device Applications Handbook gives a comprehensive snapshot of the state of the art in nanodevices for nanoelectronics applications. Combining breadth and depth, the book includes 68 chapters on topics that ...
  • Admission control for multi-tenant radio access networks 

    Pérez Romero, Jordi; Sallent Roig, José Oriol; Ferrús Ferré, Ramón Antonio; Agustí Comes, Ramon (2017)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    The sharing of Radio Access Networks is gaining momentum in small cell scenarios, due to the associated reduction in capital and operational costs. In this scenario, the split of radio resources among tenants sharing the ...
  • An Analysis of Lazy and Eager Limited Preemption Approaches under DAG-Based Global Fixed Priority Scheduling 

    Serrano, Maria A.; Melani, Alessandra; Kehr, Sebastian; Bertogna, Marko; Quiñones, Eduardo (Institute of Electrical and Electronics Engineers (IEEE), 2017-07-03)
    Comunicació de congrés
    Accés obert
    DAG-based scheduling models have been shown to effectively express the parallel execution of current many-core heterogeneous architectures. However, their applicability to real-time settings is limited by the difficulties ...
  • An Approach to a Fault Tolerance LISP Architecture 

    Martínez Manzanilla, Anny Gabriela; Ramírez, Wilson; Germán Duarte, Martín; Serral Gracià, René; Marín Tordera, Eva; Yannuzzi, Marcelo; Masip Bruin, Xavier (Springer Verlag, 2011)
    Text en actes de congrés
    Accés obert
    Next Generation Internet points out the challenge of addressing "things" on both a network with (wired) and without (wireless) infrastructure. In this scenario, new efficient and scalable addressing and routing schemes ...
  • An approximate analysis of synchronous multiple bus 

    González Peña, Luis Eduardo; Sanvicente Gargallo, Emilio (1985)
    Report de recerca
    Accés obert
    This paper presents an approximate analytic model for evaluating the performance of a loosely coupled multiprocessor architecture whose memory, organized in modules, is shared by all the processors. Each memory module (Mi) ...
  • An energy-efficient and scalable eDRAM-based register file architecture for GPGPU 

    Jing, Naifeng; Shen, Yao; Lu, Yao; Ganapathy, Shrikanth; Mao, Zhigang; Guo, Minyi; Canal Corretger, Ramon; Liang, Xiaoyao (ACM, 2013)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    The heavily-threaded data processing demands of streaming multiprocessors (SM) in a GPGPU require a large register file (RF). The fast increasing size of the RF makes the area cost and power consumption unaffordable for ...
  • An MPEG-4 performance study for non-SIMD, general purpose architectures 

    McKee, Sally A.; Fang, Zhen; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2003)
    Text en actes de congrés
    Accés obert
    MPEG-4 is an important international standard with wide applicability. This paper focuses on MPEG-4's main profile, video, whose approach allows more efficiency in coding and more flexibility in managing heterogeneous media ...
  • An on-line test strategy and analysis for a 1T1R crossbar memory 

    Escudero, Manel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Vourkas, Ioannis (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Text en actes de congrés
    Accés obert
    Memristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable ...
  • Analysis of CPI variance for dynamic binary translators/optimizers modules 

    Brankovic, Aleksandar; Stavrou, Kyriakos; Gibert Codina, Enric; González Colás, Antonio María (IEEE, 2012)
    Text en actes de congrés
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    Dynamic Binary Translators and Optimizers (DBTOs) have been established as a hot research topic. They are used in many different systems, such as emulation, instrumentation tools and innovative HW/SW co-designed ...
  • Analysis of NFV service design and management processes using ITIL and eTOM best practices 

    Nnabugwu, Samuel Nwadilobi (Universitat Politècnica de Catalunya, 2017-10-11)
    Projecte Final de Màster Oficial
    Accés obert
    The objective of this project is to analyse the design and process management of NFV and its operations using two of the most widely used and accepted best practices in telecommunication and IT industries. Focusing majorly ...