Browsing by Subject "Computer architecture"
Now showing items 1-20 of 293
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2018 International Symposium on Computer Architecture influential paper award
(2018-07-01)
Article
Open AccessThe International Symposium on Computer Architecture (ISCA) recognizes every year the most influential paper published in this conference 15 years earlier, based on its impact on research, development, products or ideas. ... -
A case study for the verification of complex timed circuits: IPCMOS
(Institute of Electrical and Electronics Engineers (IEEE), 2002)
Conference report
Open AccessThe verification of a n-stage pulse-driven IPCMOS pipeline, for any n>0, is presented. The complexity of the system is 32n transistors and delay information is provided at the level of transistor The correctness of the ... -
A control and management architecture supporting autonomic NFV services
(2019-02)
Article
Open AccessThe proposed control, orchestration and management (COM) architecture is presented from a high-level point of view; it enables the dynamic provisioning of services such as network data connectivity or generic network slicing ... -
A decoupled KILO-instruction processor
(Institute of Electrical and Electronics Engineers (IEEE), 2006)
Conference report
Open AccessBuilding processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elusive goal. Traditional processors are ... -
A fast and efficient algorithm to identify clusters in networks
(2010-11-01)
Article
Restricted access - publisher's policyA characteristic feature of many relevant real life networks, like the WWW, Internet, transportation and communication networks, or even biological and social networks, is their clustering structure. We discuss in this ... -
A general guide to applying machine learning to computer architecture
(2018)
Article
Open AccessThe resurgence of machine learning since the late 1990s has been enabled by significant advances in computing performance and the growth of big data. The ability of these algorithms to detect complex patterns in data which ... -
A hardware accelerator for ORB-SLAM
(Universitat Politècnica de Catalunya, 2019-10-17)
Master thesis
Open AccessSimultaneous Localization And Mapping (SLAM) is a key component of self-driving cars. We study ORB-SLAM, a SLAM state-of-the-art solution, and develop a hardware accelerator for a critical part of it: ORB feature extraction. ... -
A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness
(ACM, 2013)
Conference report
Open AccessComputing workloads often contain a mix of interactive, latency-sensitive foreground applications and recurring background computations. To guarantee responsiveness, interactive and batch applications are often run on ... -
A hybrid web server architecture for secure e-business web applications
(2005-09)
Article
Restricted access - publisher's policyNowadays the success of many e-commerce applications, such as on-line banking, depends on their reliability, robustness and security. Designing a web server architecture that keeps these properties under high loads is a ... -
A multi-radix approach to asynchronous division
(Institute of Electrical and Electronics Engineers (IEEE), 2001)
Conference report
Open AccessThe speed of high-radix digit-recurrence dividers is mainly determined by the hardware complexity of the quotient-digit selection function. In this paper we present a scheme that combines the area efficiency of bundled ... -
A novel register renaming technique for out-of-order processors
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Conference report
Restricted access - publisher's policyModern superscalar processors support a large number of in-flight instructions, which requires sizeable register files. Conventional register renaming techniques allocate a new storage location, i.e. physical register, for ... -
A radix-16 SRT division unit with speculation of the quotient digits
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Conference report
Open AccessThe speed of a divider based on a digit-recurrence algorithm depends mainly on the latency of the quotient digit generation function. In this paper we present an analytical approach that extends the theory developed for ... -
A resource identity management strategy for combined fog-to-cloud systems
(2018)
Conference report
Restricted access - publisher's policyFog-to-Cloud (F2C) is an emerging architecture intended to manage the resources continuum from far datacenters up to the near edge, putting together the cloud and fog concepts. It aims to obtain both, an efficient utilization ... -
A Rudimentary Machine. Experiences in the Design of a Pedagogic Computer
(Publicat en web, 1999-07)
Article
Open AccessThis paper describes a pedagogic computer named \M aquina Rudimentaria". This computer has been de- signed to be used in a rst course on logic design or com- puter architecture; orthogonality and simplicity have been the ... -
A self-adaptive hardware architecture with fault tolerance capabilities
(2013-12-09)
Article
Restricted access - publisher's policyThis paper describes a Fault Tolerance System (FTS) implemented in a new self-adaptive hardware architecture. This architecture is based on an array of cells that implements in a distributed way self-adaptive capabilities. ... -
A sensor web architecture for integrating smart oceanographic sensors into the semantic sensor web
(2018-10)
Article
Open AccessEffective ocean and coastal data management are needed to manage marine ecosystem health. Past ocean and coastal data management systems were often very specific to a particular application and region, but this focused ... -
A software-hardware hybrid steering mechanism for clustered microarchitectures
(Institute of Electrical and Electronics Engineers (IEEE), 2008)
Conference report
Open AccessClustered microarchitectures provide a promising paradigm to solve or alleviate the problems of increasing microprocessor complexity and wire delays. High- performance out-of-order processors rely on hardware-only steering ... -
A systolic algorithm for the fast computation of the connected components of a graph
(Institute of Electrical and Electronics Engineers (IEEE), 1988)
Conference report
Open AccessThe authors consider the description of a systolic algorithm to solve the connected-component problem. It is executed in a ring topology with N processors, requiring O(Nlog N) time without regard to the graph's sparsity. ... -
A Tensor Marshaling Unit for sparse tensor algebra on general-purpose processors
(Association for Computing Machinery (ACM), 2023)
Conference report
Open AccessThis paper proposes the Tensor Marshaling Unit (TMU), a near-core programmable dataflow engine for multicore architectures that accelerates tensor traversals and merging, the most critical op-erations of sparse tensor ... -
A trace-scaling agent for parallel application tracing
(Institute of Electrical and Electronics Engineers (IEEE), 2002)
Conference report
Open AccessTracing and performance analysis tools are an important component in the development of high performance applications. Tracing parallel programs with current tracing tools, however, easily leads to large trace files with ...
