Now showing items 1-20 of 40

  • A fast and retargetable framework for logic-IP-internal electromigration assessment comprehending advanced waveform effects 

    Jain, Palkesh; Cortadella, Jordi; Sapatnekar, Sachin S. (2016-06-01)
    Article
    Open Access
    A new methodology for system-on-chip-level logic-IP-internal electromigration verification is presented in this paper, which significantly improves accuracy by comprehending the impact of the parasitic RC loading and ...
  • A general model for performance optimization of sequential systems 

    Bufistov, Dmitry; Cortadella, Jordi; Kishinevsky, Michael; Sapatnekar, Sachin S. (Institute of Electrical and Electronics Engineers (IEEE), 2007)
    Conference report
    Open Access
    Retiming, c-slow retiming and recycling are different transformations for the performance optimization of sequential circuits. For retiming and c-slow retiming, different models that provide exact solutions have already ...
  • A hierarchical mathematical model for automatic pipelining and allocation using elastic systems 

    Cortadella, Jordi; Petit Silvestre, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Conference report
    Open Access
    The advent of FPGA-based accelerators has encouraged the use of high-level synthesis (HLS) for rapid prototyping and design space exploration. In this context, design optimization at behavioral level becomes a critical ...
  • A multi-radix approach to asynchronous division 

    Cornetta, Gianluca; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2001)
    Conference report
    Open Access
    The speed of high-radix digit-recurrence dividers is mainly determined by the hardware complexity of the quotient-digit selection function. In this paper we present a scheme that combines the area efficiency of bundled ...
  • A new look at the conditions for the synthesis of speed-independent circuits 

    Pastor Llorens, Enric; Cortadella, Jordi; Roig Mansilla, Oriol (Institute of Electrical and Electronics Engineers (IEEE), 1995)
    Conference report
    Open Access
    This paper presents a set of sufficient conditions for the gate-level synthesis of speed-independent circuits when constrained to a given class of gate library. Existing synthesis methodologies are restricted to architectures ...
  • An experimental approach to Memristive Devices and its applications on Stateful Logic : Design and experimental evaluation of the IMPLY logic gate with Knowm memristors 

    Galofre Ballbe, Aina Elisabeth (Universitat Politècnica de Catalunya, 2017-06-15)
    Bachelor thesis
    Open Access
    Recent discovery (2008) of the non-volatile binary resistances known as memristors has attracted new scientific research opportunities. These include novel approaches to present-day technology such as memory storage, ...
  • A radix-16 SRT division unit with speculation of the quotient digits 

    Gianluca, Cornetta; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Conference report
    Open Access
    The speed of a divider based on a digit-recurrence algorithm depends mainly on the latency of the quotient digit generation function. In this paper we present an analytical approach that extends the theory developed for ...
  • A single event transient hardening circuit design technique based on strengthening 

    Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2013)
    Conference report
    Restricted access - publisher's policy
    In a near future of high-density and low-power technologies, the study of soft errors will not only be relevant for memory systems and latches of logic circuits, but also for the combinational parts of logic circuits which ...
  • Conception d'un filtre Analogique / Numérique 

    Zhang, Xipeng (Universitat Politècnica de Catalunya, 2013-09-10)
    Master thesis
    Open Access
    [ANGLÈS] In this thesis, a tunable analog filter with digital control is presented. The digital control is implemented by means of a Spartan 3A FPGA and programmable resistors. The system consists of two identical tunable ...
  • Coping with the variability of combinational logic delays 

    Cortadella, Jordi; Kondratyev, Alex; Lavagno, Luciano; Sotiriou, Christos P. (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Conference report
    Open Access
    This paper proposes a technique for creating a combinational logic network with an output that signals when all other outputs have stabilized. The method is based on dual-rail encoding, and guarantees low timing overhead ...
  • Correct-by-construction microarchitectural pipelining 

    Kam, Timothy; Kishinevsky, Michael; Cortadella, Jordi; Galcerán Oms, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Conference report
    Open Access
    This paper presents a method for correct-by-construction microarchitectural pipelining that handles cyclic systems with dependencies between iterations. Our method combines previously known bypass and retiming transformations ...
  • Decomposition and technology mapping of speed-independent circuits using Boolean relations 

    Cortadella, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Pastor Llorens, Enric; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1997)
    Conference report
    Open Access
    Presents a new technique for the decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available in ...
  • Decomposition and technology mapping of speed-independent circuits using Boolean relations 

    Cortadella, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Pastor Llorens, Enric; Yakovlev, Alex (1999-09)
    Article
    Open Access
    This paper presents a new technique for decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available ...
  • Designing asynchronous circuits from behavioural specifications with internal conflicts 

    Cortadella, Jordi; Lavagno, Luciano; Vanbekbergen, Peter; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1994)
    Conference report
    Open Access
    The paper presents a systematic method for synthesizing asynchronous circuits from event-based specifications with conflicts on output signals. It describes a set of semantic-preserving transformations performed at the ...
  • Division with speculation of quotient digits 

    Cortadella, Jordi; Lang, Tomás (Institute of Electrical and Electronics Engineers (IEEE), 1993)
    Conference report
    Open Access
    The speed of SRT-type dividers is mainly determined by the complexity of the quotient-digit selection, so that implementations are limited to low-radix stages. A scheme is presented in which the quotient-digit is speculated ...
  • Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies 

    Barredo Ferreira, Adrián; Cebrián González, Juan Manuel; Valero Cortés, Mateo; Casas Guix, Marc; Moreto Planas, Miquel (2020-03)
    Article
    Open Access
    Moore’s Law predicted that the number of transistors on a chip would double approximately every 2 years. However, this trend is arriving at an impasse. Optimizing the usage of the available transistors within the thermal ...
  • Evaluating A+B=K conditions in constant time 

    Cortadella, Jordi; Llaberia Griñó, José M. (Institute of Electrical and Electronics Engineers (IEEE), 1988)
    Conference report
    Open Access
    The authors consider a type of condition that can be evaluated without requiring a complete ALU (arithmetic logic unit) operation. The circuit that is presented detects the condition A+B=K (n-bit numbers) in constant time, ...
  • Evaluation of A+B=K conditions without carry propagation 

    Cortadella, Jordi; Llaberia Griñó, José M. (Institute of Electrical and Electronics Engineers (IEEE), 1992-11)
    Article
    Open Access
    The response time of parallel adders is mainly determined by the carry propagation delay. The evaluation of conditions of the type A+B=K is addressed. Although an addition is involved in the comparison, it is shown that ...
  • From synchronous to asynchronous: an automatic approach 

    Cortadella, Jordi; Kondratyev, Alex; Lavagno, Luciano; Lwin, Kelvin; Sotiriou, Christos P. (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Conference report
    Open Access
    This paper presents a methodology to derive asynchronous circuits from optimized synchronous circuits by replacing the clock distribution tree by a handshaking network. A case study shows the applicability of the method ...
  • Hierarchical gate-level verification of speed-independent circuits 

    Roig Mansilla, Oriol; Cortadella, Jordi; Pastor Llorens, Enric (Institute of Electrical and Electronics Engineers (IEEE), 1995)
    Conference report
    Open Access
    This paper presents a method for the verification of speed-independent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on ...