Browsing by Subject "Circuits integrats"
Now showing items 1-20 of 338
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105. Impuls a les tecnologies de la informació i la comunicació a la UPC
(Oficina de Comunicació i Relació amb els Mitjans, 1998-11)
Article
Open Access -
3D-printed UHF-RFID tag for embedded applications
(Institute of Electrical and Electronics Engineers (IEEE), 2020-08-10)
Article
Open AccessThis paper presents the design, manufacture and characterization of a novel 3D passive UHF-RFID tag for embedded applications. The prototype is fabricated using additive manufacturing techniques: 3D printing and copper ... -
5GHz CMOS all-pass filter-based true time delay cell
(2018-12-22)
Article
Open AccessAnalog CMOS time-delay cells realized by passive components, e.g., lumped LC delay lines, are inefficient in terms of area for multi-GHz frequencies. All-pass filters considered as active circuits can, therefore, be the ... -
A case study for the verification of complex timed circuits: IPCMOS
(Institute of Electrical and Electronics Engineers (IEEE), 2002)
Conference report
Open AccessThe verification of a n-stage pulse-driven IPCMOS pipeline, for any n>0, is presented. The complexity of the system is 32n transistors and delay information is provided at the level of transistor The correctness of the ... -
A circuit-level SPICE modeling strategy for the simulation of behavioral variability in ReRAM
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Conference report
Open AccessThe intrinsic behavioral variability in resistive switching devices (also known as 'memristors' or 'ReRAM devices') can be a reliability limiting factor or an opportunity for applications where randomness of resistance ... -
A compact switched-capacitor multi-bit quantizer for low-power high-resolution delta-sigma ADCs
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Conference lecture
Restricted access - publisher's policyThis paper proposes a compact switched-capacitor (SC) multi-bit flash quantizer for low-power high-resolution delta-sigma modulators (¿SMs). First, a general power model for single-loop ¿SMs is presented to show the ... -
A comparison of PUF cores suitable for FPGA devices
(2016-11-14)
Conference report
Open AccessA PUF extracts a unique identifier per die using physical random variation caused by variability of the manufacturing process. PUFs can be used for hardware authentication, but also as generators of confidential keys. ... -
A comprehensive high-level model for CMOS-MEMS resonators
(2018-01-24)
Article
Open AccessThis paper presents a behavioral modeling technique for CMOS microelectromechanical systems (MEMS) microresonators that enables simulation of an MEMS resonator model in Analog Hardware Description Language format within a ... -
A crosstalk latch circuit design
(Institute of Electrical and Electronics Engineers (IEEE), 1990)
Conference report
Restricted access - publisher's policyA D-latch sequential circuit design is presented that exhibits an elevated degree of tolerance to common and differential mode noise in the clock lines. The circuit tolerates noise voltages in the clock signals in the range ... -
A detailed methodology to compute soft error rates in advanced technologies
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Restricted access - publisher's policySystem reliability has become a key design aspect for computer systems due to the aggressive technology miniaturization. Errors are typically dominated by transient faults due to radiation and are strongly related to the ... -
A forming-free ReRAM cell with low operating voltage
(2020-11-25)
Article
Open AccessThe unwanted electro-forming process is unavoidable for the practical application of most resistive random access memory (ReRAM) devices, which is always being one of the obstacles for the massive commercialization of this ... -
A highly-accurate low-power CMOS potentiostat for implantable biosensors
(IEEE, 2011)
Conference report
Restricted access - publisher's policyCurrent-mirror-based potentiostats suffer from systematic and random errors causing offset, gain and linearity error in reading out the sensor data. In this work, a new potentiostat topology is proposed to eliminate the ... -
A Low-Cost Unified Experimental FPGA Board for Cryptography Applications
(2016-11-16)
Conference report
Open AccessThis paper describes the evaluation of available experimental boards, the comparison of their supported set of experiments and other aspects. The second part of this evaluation is focused on the design process of the ... -
A multi-synchronous bi-directional NoC (MBiNoC) architecture with dynamic self-reconfigurable channel for the GALS infrastructure
(Elsevier, 2017-03-16)
Article
Open AccessAbstract To enhance the performance of on-chip communications of Globally Asynchronous Locally Synchronous Systems (GALS), a dynamic reconfigurable multi-synchronous router architecture is proposed to increase network on ... -
A new probabilistic design methodology of nanoscale digital circuits
(IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
Conference report
Restricted access - publisher's policyThe continuing trends of device scaling and increase in complexity towards terascale system on chip level of integration are putting growing difficulties into several areas of design. The intrinsic variability problem is ... -
A pragmatic gaze on stochastic resonance based variability tolerant memristance
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Conference report
Open AccessStochastic Resonance (SR) is a nonlinear system specific phenomenon, which was demonstrated to lead to system unexpected (counter-intuitive) performance improvements under certain noise conditions. Memristor, on the other ... -
A Reliable Low-area Low-power PUF-based Key Generator
(2016-11-14)
Conference report
Open AccessThis paper reports the implementation of a lowarea low-power 128-bit PUF-based key generation module which exploits a novel Two-Stage IDentification (TSID) cell showing a higher noise immunity then a standard SRAM cell. ... -
A reprogrammable graphene nanoribbon-based logic gate
(2023)
Article
Open AccessIn this article, taking into consideration the exceptional technological properties of a unique 2-D material, namely Graphene, we are envisioning its usage as the structure material of a non-back-gated re-programmable ... -
A Self-Repairable TRNG
(2016-11-14)
Conference report
Open Access -
A systematic method to design efficient ternary high performance CNTFET-based logic cells
(Institute of Electrical and Electronics Engineers (IEEE), 2020-01-01)
Article
Open AccessThe huge quantity of nodes and interconnections in modern binary circuits leads to extremely high levels of energy consumption. The interconnection complexity and other issues of binary circuits encourage researchers to ...