Now showing items 1-20 of 189

  • 105. Impuls a les tecnologies de la informació i la comunicació a la UPC 

    Universitat Politècnica de Catalunya. Rectorat (Oficina de Comunicació i Relació amb els Mitjans, 1998-11)
    Article
    Open Access
  • 5GHz CMOS all-pass filter-based true time delay cell 

    Aghazadeh, Seyed Rasoul; Martínez García, Herminio; Saberkari, Alireza (2018-12-22)
    Article
    Open Access
    Analog CMOS time-delay cells realized by passive components, e.g., lumped LC delay lines, are inefficient in terms of area for multi-GHz frequencies. All-pass filters considered as active circuits can, therefore, be the ...
  • A case study for the verification of complex timed circuits: IPCMOS 

    Peña Basurto, Marco Antonio; Cortadella, Jordi; Pastor Llorens, Enric; Smirnov, Alexandre (Institute of Electrical and Electronics Engineers (IEEE), 2002)
    Conference report
    Open Access
    The verification of a n-stage pulse-driven IPCMOS pipeline, for any n>0, is presented. The complexity of the system is 32n transistors and delay information is provided at the level of transistor The correctness of the ...
  • A comparison of PUF cores suitable for FPGA devices 

    Mureddu, Ugo; Bossuet, Lilian; Fischer, Viktor (2016-11-14)
    Conference report
    Open Access
    A PUF extracts a unique identifier per die using physical random variation caused by variability of the manufacturing process. PUFs can be used for hardware authentication, but also as generators of confidential keys. ...
  • A comprehensive high-level model for CMOS-MEMS resonators 

    Banerji, Saoni; Fernández, Daniel; Madrenas Boadas, Jordi (2018-01-24)
    Article
    Open Access
    This paper presents a behavioral modeling technique for CMOS microelectromechanical systems (MEMS) microresonators that enables simulation of an MEMS resonator model in Analog Hardware Description Language format within a ...
  • A crosstalk latch circuit design 

    Rubio Sola, Jose Antonio; Pons Nin, Joan; Anglada, Raimon (Institute of Electrical and Electronics Engineers (IEEE), 1990)
    Conference report
    Restricted access - publisher's policy
    A D-latch sequential circuit design is presented that exhibits an elevated degree of tolerance to common and differential mode noise in the clock lines. The circuit tolerates noise voltages in the clock signals in the range ...
  • A detailed methodology to compute soft error rates in advanced technologies 

    Riera Villanueva, Marc; Canal Corretger, Ramon; Abella, Jaume; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Restricted access - publisher's policy
    System reliability has become a key design aspect for computer systems due to the aggressive technology miniaturization. Errors are typically dominated by transient faults due to radiation and are strongly related to the ...
  • Advanced failure detection techniques in deep submicron CMOS integrated circuits 

    Rubio Sola, Jose Antonio; Altet Sanahujes, Josep; Mateo Peña, Diego (Pergamon Press, 2009)
    Conference report
    Restricted access - publisher's policy
    The test of present integrated circuits exhibits many confining aspects, among them the adequate selection of the observable variables, the use of combined testing approaches, an each time more restricted controllability ...
  • A highly-accurate low-power CMOS potentiostat for implantable biosensors 

    Razzaghpour, Milad; Rodriguez Duenas, Saul; Alarcón Cot, Eduardo José; Rusu, Ana (IEEE, 2011)
    Conference report
    Restricted access - publisher's policy
    Current-mirror-based potentiostats suffer from systematic and random errors causing offset, gain and linearity error in reading out the sensor data. In this work, a new potentiostat topology is proposed to eliminate the ...
  • A Low-Cost Unified Experimental FPGA Board for Cryptography Applications 

    Bartík, Matěj; Buček, Jiří (2016-11-16)
    Conference report
    Open Access
    This paper describes the evaluation of available experimental boards, the comparison of their supported set of experiments and other aspects. The second part of this evaluation is focused on the design process of the ...
  • A multi-synchronous bi-directional NoC (MBiNoC) architecture with dynamic self-reconfigurable channel for the GALS infrastructure 

    Kamal, Rajeev; Moreno Aróstegui, Juan Manuel (Elsevier, 2017-03-16)
    Article
    Open Access
    Abstract To enhance the performance of on-chip communications of Globally Asynchronous Locally Synchronous Systems (GALS), a dynamic reconfigurable multi-synchronous router architecture is proposed to increase network on ...
  • An alternative approach to model the internal activity of integrated circuits. 

    Berbel Artal, Néstor; Fernández García, Raúl; Gil Galí, Ignacio; Li, Binhong; BenDhia, S.; Boyer, A. (2012)
    Conference report
    Open Access
    This paper deals with the EMC modeling of integrated circuits and the standardized model IEC 62433-2 (Integrated Circuit Emission Model – Conducted Emission [1]). This standardized model has been applied into a basic digital ...
  • Analysis and evaluation of using a tuning inductance on the performance of gilbert cell-based CMOS sub-harmonic mixer 

    Saberkari, Alireza; Shokouhi, Shahriar B.; Alarcón Cot, Eduardo José; Baghersalimi, Gholamreza (2012)
    Article
    Restricted access - publisher's policy
    The effect of using a tuning inductance on the performance of a Gilbert cell-based two level transistor CMOS sub-harmonic mixer is investigated. The tuning inductor used between the RF and LO switching stages causes ...
  • Analysis and modelling of parasitic substrate coupling in CMOS circuits 

    Aragonès Cervera, Xavier; Moll Echeto, Francisco de Borja; Roca Adrover, Miquel; Rubio Sola, Jose Antonio (1995-10)
    Article
    Restricted access - publisher's policy
    Analysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling ...
  • Analysis of SoftError Rates for future technologies 

    Riera Villanueva, Marc (Universitat Politècnica de Catalunya, 2015-07)
    Master thesis
    Open Access
    La fiabilitat s'ha convertit en un aspecte important del disseny de sistemes informàtics a causa de la miniaturització de la tecnologia. En aquest projecte s'analitza la fiabilitat de les tecnologies actuals i futures ...
  • Analyzing stability concerns in the presence of variations in Subthreshold SRAM 

    Rana, Manish (Universitat Politècnica de Catalunya, 2012-07-02)
    Master thesis
    Open Access
    In this work, we analyse the stability of the SRAM bitcells when operating in subthreshold supply voltages.We propose a new bit cell with higher stability than 6T Bitcell,that is able to discharge the bit lines in 41% less ...
  • A new probabilistic design methodology of nanoscale digital circuits 

    García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
    Conference report
    Restricted access - publisher's policy
    The continuing trends of device scaling and increase in complexity towards terascale system on chip level of integration are putting growing difficulties into several areas of design. The intrinsic variability problem is ...
  • An on-line test strategy and analysis for a 1T1R crossbar memory 

    Escudero, Manel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Vourkas, Ioannis (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Conference report
    Open Access
    Memristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable ...
  • An ultra low-power mixed-signal back-end for passive sensor UHF RFID transponders 

    Rodriguez, J.; Delgado Restituto, M.; Masuch, J.; Rodriguez Perez, Alberto; Alarcón Cot, Eduardo José; Rodríguez Vázquez, Ángel (IEEE Press. Institute of Electrical and Electronics Engineers, 2012-02)
    Article
    Restricted access - publisher's policy
    This paper describes the design of mixed-signal back end for an ultrahigh-frequency sensor-enabled radio-frequency identification transponder in full compliance with the Electronic Product Code Class-1 Generation-2 protocol, ...
  • A pragmatic gaze on stochastic resonance based variability tolerant memristance 

    Ntinas, Vasileios; Rubio Sola, Jose Antonio; Sirakoulis, Georgios Ch.; Cotofana, Sorin (Institute of Electrical and Electronics Engineers (IEEE), 2019)
    Conference report
    Open Access
    Stochastic Resonance (SR) is a nonlinear system specific phenomenon, which was demonstrated to lead to system unexpected (counter-intuitive) performance improvements under certain noise conditions. Memristor, on the other ...