Now showing items 1-20 of 58

  • A multi-radix approach to asynchronous division 

    Cornetta, Gianluca; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2001)
    Conference report
    Open Access
    The speed of high-radix digit-recurrence dividers is mainly determined by the hardware complexity of the quotient-digit selection function. In this paper we present a scheme that combines the area efficiency of bundled ...
  • A region-based theory for state assignment in speed-independent circuits 

    Cortadella, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Yakovlev, Alex (1997-08)
    Article
    Open Access
    State assignment problems still need satisfactory solutions to make asynchronous circuit synthesis more practical. A well-known example of such a problem is that of complete state coding (CSC), which happens when a pair ...
  • A structural encoding technique for the synthesis of asynchronous circuits 

    Carmona Vargas, Josep; Cortadella, Jordi; Pastor Llorens, Enric (Institute of Electrical and Electronics Engineers (IEEE), 2001)
    Conference report
    Open Access
    This paper presents a method for the automatic synthesis of asynchronous circuits from Petri net specifications. The method is based on a structural encoding of the system in such a way that a circuit implementation is ...
  • Asynchronous multipliers with variable-delay counters 

    Cornetta, Gianluca; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2001)
    Conference report
    Open Access
    Although multiplication is an intensely studied arithmetic operation and many fast algorithms and implementations are available, it still represents one of the major bottlenecks of many digital systems that require intensive ...
  • Automatic generation of synchronous test patterns for asynchronous circuits 

    Roig Mansilla, Oriol; Cortadella, Jordi; Peña Basurto, Marco Antonio; Pastor Llorens, Enric (Institute of Electrical and Electronics Engineers (IEEE), 1997)
    Conference report
    Open Access
    This paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exercised by applying synchronous test vectors, ...
  • Automatic synthesis and optimization of partially specified asynchronous systems 

    Kondratyev, Alex; Cortadella, Jordi; Kishinevsky, Michael; Lavagno, Luciano; Yakovlev, Alex (Association for Computing Machinery (ACM), 1999)
    Conference report
    Open Access
    A method for automating the synthesis of asynchronous control circuits from high level (CSP-like) and/or partial STG (involving only functionally critical events) specifications is presented. The method solves two key ...
  • Behavioral transformations to increase the noise immunity of asynchronous specifications 

    Taubin, Alexander; Kondratyev, Alex; Cortadella, Jordi; Lavagno, Luciano (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Conference report
    Open Access
    Noise immunity is becoming one of the most important design parameters for deep-sub-micron (DSM) technologies. Asynchronous circuits seem to be a good candidate to alleviate the problems originated by simultaneous switching ...
  • Bridging modularity and optimality: delay-insensitive interfacing in asynchronous circuits synthesis 

    Saito, Hiroshi; Kondratyev, Alex; Cortadella, Jordi; Lavagno, Luciano; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Conference report
    Open Access
    Two trends are of major concern for digital circuit designers: the relative increase of interconnect delays with respect to gate delays and the demand for design reuse. Both pose difficult problems to synchronous design ...
  • CAD directions for high performance asynchronous circuits 

    Stevens, Kenneth S.; Rotem, Shai; Burns, Steven M.; Cortadella, Jordi; Ginosar, Ran; Kishinevsky, Michael; Roncken, Marly (Association for Computing Machinery (ACM), 1999)
    Conference report
    Open Access
    This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using relative timing. This methodology was developed for a prototype iA32 ...
  • Checking signal transition graph implementability by symbolic bdd traversal 

    Kondratyev, Alex; Cortadella, Jordi; Kishinevsky, Michael; Pastor Llorens, Enric; Roig Mansilla, Oriol; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1995)
    Conference report
    Open Access
    This paper defines conditions for a Signal Transition Graph to be implemented by an asynchronous circuit. A hierarchy of the implementability classes is presented. Our main concern is the implementability of the specification ...
  • Clustering for the optimisation of asynchronous controllers 

    Casanova Bachs, Jonàs (Universitat Politècnica de Catalunya, 2008-06-25)
    Master thesis
    Open Access
  • Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits 

    Peña Basurto, Marco Antonio; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 1996)
    Conference report
    Open Access
    This paper presents a new methodology to automatically synthesize asynchronous circuits from descriptions based on process algebra. Traditionally, syntax-directed techniques have been used to generate a netlist of basic ...
  • Complete state encoding based on the theory of regions 

    Cortadella, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1996)
    Conference report
    Open Access
    Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) and/or State Graphs (SGs) involves solving state coding problems. A well-known example of such problems is that of Complete State Coding (CSC), which ...
  • Concurrency primitives in Haskell 

    Martí I Peiró, Daniel (Universitat Politècnica de Catalunya, 2016-06-27)
    Bachelor thesis
    Open Access
    Covenantee:  University of Newcastle upon Tyne
  • Coping with the variability of combinational logic delays 

    Cortadella, Jordi; Kondratyev, Alex; Lavagno, Luciano; Sotiriou, Christos P. (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Conference report
    Open Access
    This paper proposes a technique for creating a combinational logic network with an output that signals when all other outputs have stabilized. The method is based on dual-rail encoding, and guarantees low timing overhead ...
  • Decomposition and technology mapping of speed-independent circuits using Boolean relations 

    Cortadella, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Pastor Llorens, Enric; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1997)
    Conference report
    Open Access
    Presents a new technique for the decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available in ...
  • Decomposition and technology mapping of speed-independent circuits using Boolean relations 

    Cortadella, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Pastor Llorens, Enric; Yakovlev, Alex (1999-09)
    Article
    Open Access
    This paper presents a new technique for decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available ...
  • Designing asynchronous circuits from behavioural specifications with internal conflicts 

    Cortadella, Jordi; Lavagno, Luciano; Vanbekbergen, Peter; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1994)
    Conference report
    Open Access
    The paper presents a systematic method for synthesizing asynchronous circuits from event-based specifications with conflicts on output signals. It describes a set of semantic-preserving transformations performed at the ...
  • Design of a column decoder for a binary vision sensor implementing run length encoding 

    Gimenéz Umbert, Bruno (Universitat Politècnica de Catalunya / Università degli Studi di Trento, 2014)
    Bachelor thesis
    Open Access
    Covenantee:  Università degli studi di Trento
    This work describes the architecture of an asynchronous column decoder for a CMOS binary vision sensor. The decoder compresses and code data, at row-level, before delivering off-chip. The operation is completely asynchronous ...
  • Desynchronization: Synthesis of asynchronous circuits from synchronous specifications 

    Cortadella, Jordi; Kondratyev, Alex; Lavagno, Luciano; Sotiriou, Christos (2006-10)
    Article
    Open Access
    Asynchronous implementation techniques, which measure logic delays at runtime and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst case delays at design ...