Browsing by Author "Cazorla, Francisco"
Now showing items 1-20 of 22
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Adapting cache partitioning algorithms to pseudo-LRU replacement policies
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
Conference report
Open AccessRecent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache partitioning algorithms proposed so far assume Least ... -
A dynamic scheduler for balancing HPC applications
(Institute of Electrical and Electronics Engineers (IEEE), 2008)
Conference report
Open AccessLoad imbalance cause significant performance degradation in High Performance Computing applications. In our previous work we showed that load imbalance can be alleviated by modern MT processors that provide mechanisms for ... -
A flexible heterogeneous multi-core architecture
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Conference report
Open AccessMulti-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a challenge as application mixes in this ... -
A two level load/store queue based on execution locality
(Institute of Electrical and Electronics Engineers (IEEE), 2008)
Conference report
Open AccessMulticore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be increasingly limited by the remaining sequential ... -
Balancing HPC applications through smart allocation of resources in MT processors
(Institute of Electrical and Electronics Engineers (IEEE), 2008)
Conference report
Open AccessMany studies have shown that load imbalancing causes significant performance degradation in High Performance Computing (HPC) applications. Nowadays, Multi-Threaded (MT1) processors are widely used in HPC for their good ... -
CPU accounting in CMP processors
(2009-01)
Article
Open AccessChip-MultiProcessors (CMP) introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is ... -
Explaining dynamic cache partitioning speed ups
(2007-01)
Article
Open AccessCache partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, ... -
FAME: FAirly MEasuring multithreaded architectures
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Conference report
Open AccessNowadays, multithreaded architectures are becoming more and more popular. In order to evaluate their behavior, several methodologies and metrics have been proposed. A methodology defines when the measurements of a given ... -
ITCA: Inter-Task Conflict-Aware CPU accounting for CMPs
(IEEE Computer Society, 2009)
Conference report
Open AccessChip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism from an application. CMPs introduce complexities ... -
Kilo-instruction processors: overcoming the memory wall
(2005-05)
Article
Open AccessHistorically, advances in integrated circuit technology have driven improvements in processor microarchitecture and led to todays microprocessors with sophisticated pipelines operating at very high clock frequencies. ... -
Mitigating software-instrumentation cache effects in measurement-based timing analysis
(Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2016)
Conference report
Open AccessMeasurement-based timing analysis (MBTA) is often used to determine the timing behaviour of software programs embedded in safety-aware real-time systems deployed in various industrial domains including automotive and ... -
Multicore resource management
(2008-06)
Article
Open AccessCurrent resource management mechanisms and policies are inadequate for future multicore systems. Instead, a hardware/software interface based on the virtual private machine abstraction would allow software policies to ... -
Online prediction of applications cache utility
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Conference report
Open AccessGeneral purpose architectures are designed to offer average high performance regardless of the particular application that is being run. Performance and power inefficiencies appear as a consequence for some programs. ... -
On the assessment of probabilistic WCET estimates reliability for arbitrary programs
(2017-04-11)
Article
Open AccessMeasurement-Based Probabilistic Timing Analysis (MBPTA) has been shown to be an industrially viable method to estimate the Worst-Case Execution Time (WCET) of real-time programs running on processors including several ... -
On the problem of evaluating the performance of multiprogrammed workloads
(2010-12)
Article
Open AccessMultithreaded architectures are becoming more and more popular. In order to evaluate their behavior, several methodologies and metrics have been proposed. A methodology defines when the measurements for a given workload ... -
On the problem of minimizing workload execution time in SMT processors
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Conference report
Open AccessMost research work on (simultaneous multithreading processors) SMTs focuses on improving throughput and/or fairness, or on prioritizing some threads over others in a workload. In this paper, we discuss a new problem not ... -
Per-task energy accounting in computing systems
(2013)
External research report
Open AccessWe present for the first time the concept of per-task energy accounting (PTEA) and relate it to per-task energy metering (PTEM). We show the benefits of supporting both in future computing systems. Using the shared last-level ... -
Predictable performance in SMT processors: synergy between the OS and SMTs
(2006-07)
Article
Open AccessCurrent operating systems (OS) perceive the different contexts of simultaneous multithreaded (SMT) processors as multiple independent processing units, although, in reality, threads executed in these units compete for the ... -
Probabilistic timing analysis on time-randomized platforms for the space domain
(Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
Conference lecture
Open AccessTiming Verification is a fundamental step in real-time embedded systems, with measurement-based timing analysis (MBTA) being the most common approach used to that end. We present a Space case study on a real platform that ... -
SEDEA: A sensible approach to account DRAM energy in multicore systems
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Conference report
Open AccessAs the energy cost in todays computing systems keeps increasing, measuring the energy becomes crucial in many scenarios. For instance, due to the fact that the operational cost of datacenters largely depends on the energy ...
