• Adapting cache partitioning algorithms to pseudo-LRU replacement policies 

    Kedzierski, Kamil; Moreto Planas, Miquel; Cazorla, Francisco; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2010)
    Texto en actas de congreso
    Acceso abierto
    Recent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache partitioning algorithms proposed so far assume Least ...
  • A dynamic scheduler for balancing HPC applications 

    Boneti, Carlos; Gioiosa, Roberto; Cazorla, Francisco; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Texto en actas de congreso
    Acceso abierto
    Load imbalance cause significant performance degradation in High Performance Computing applications. In our previous work we showed that load imbalance can be alleviated by modern MT processors that provide mechanisms for ...
  • A flexible heterogeneous multi-core architecture 

    Pericàs Gleim, Miquel; Cristal Kestelman, Adrián; Cazorla, Francisco; González García, Rubén; Jiménez, Daniel A.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2007)
    Texto en actas de congreso
    Acceso abierto
    Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a challenge as application mixes in this ...
  • A two level load/store queue based on execution locality 

    Pericàs Gleim, Miquel; Cristal Kestelman, Adrián; Cazorla, Francisco; González García, Rubén; Veidenbaum, Alexander V; Jiménez, Daniel A.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Texto en actas de congreso
    Acceso abierto
    Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be increasingly limited by the remaining sequential ...
  • Balancing HPC applications through smart allocation of resources in MT processors 

    Boneti, Carlos; Gioiosa, Roberto; Cazorla, Francisco; Corbalán González, Julita; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Texto en actas de congreso
    Acceso abierto
    Many studies have shown that load imbalancing causes significant performance degradation in High Performance Computing (HPC) applications. Nowadays, Multi-Threaded (MT1) processors are widely used in HPC for their good ...
  • CPU accounting in CMP processors 

    Luque, Carlos; Moreto Planas, Miquel; Cazorla, Francisco; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortés, Mateo (2009-01)
    Artículo
    Acceso abierto
    Chip-MultiProcessors (CMP) introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is ...
  • Explaining dynamic cache partitioning speed ups 

    Moreto Planas, Miquel; Cazorla, Francisco; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2007-01)
    Artículo
    Acceso abierto
    Cache partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, ...
  • FAME: FAirly MEasuring multithreaded architectures 

    Vera, Javier; Cazorla, Francisco; Pajuelo González, Manuel Alejandro; Santana Jaria, Oliverio J.; Fernandez Garcia, Enrique; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2007)
    Texto en actas de congreso
    Acceso abierto
    Nowadays, multithreaded architectures are becoming more and more popular. In order to evaluate their behavior, several methodologies and metrics have been proposed. A methodology defines when the measurements of a given ...
  • ITCA: Inter-Task Conflict-Aware CPU accounting for CMPs 

    Luque, Carlos; Moreto Planas, Miquel; Cazorla, Francisco; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortés, Mateo (IEEE Computer Society, 2009)
    Texto en actas de congreso
    Acceso abierto
    Chip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism from an application. CMPs introduce complexities ...
  • Kilo-instruction processors: overcoming the memory wall 

    Cristal Kestelman, Adrián; Santana Jaria, Oliverio J.; Cazorla, Francisco; Galluzzi, Marco; Ramirez Garcia, Tanausú; Pericas, Miquel; Valero Cortés, Mateo (2005-05)
    Artículo
    Acceso abierto
    Historically, advances in integrated circuit technology have driven improvements in processor microarchitecture and led to todays microprocessors with sophisticated pipelines operating at very high clock frequencies. ...
  • Mitigating software-instrumentation cache effects in measurement-based timing analysis 

    Díaz, Enrique; Abella, Jaume; Mezzetti, Enrico; Aguirre, Irune; Azkarate-Askasua, Mikel; Vardanega, Tullio; Cazorla, Francisco (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2016)
    Texto en actas de congreso
    Acceso abierto
    Measurement-based timing analysis (MBTA) is often used to determine the timing behaviour of software programs embedded in safety-aware real-time systems deployed in various industrial domains including automotive and ...
  • Multicore resource management 

    Nesbit, Kyle J.; Smith, James E.; Moreto Planas, Miquel; Cazorla, Francisco; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2008-06)
    Artículo
    Acceso abierto
    Current resource management mechanisms and policies are inadequate for future multicore systems. Instead, a hardware/software interface based on the virtual private machine abstraction would allow software policies to ...
  • Online prediction of applications cache utility 

    Moreto Planas, Miquel; Cazorla, Francisco; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2007)
    Texto en actas de congreso
    Acceso abierto
    General purpose architectures are designed to offer average high performance regardless of the particular application that is being run. Performance and power inefficiencies appear as a consequence for some programs. ...
  • On the assessment of probabilistic WCET estimates reliability for arbitrary programs 

    Milutinovic, Suzana; Abella, Jaume; Cazorla, Francisco (2017-04-11)
    Artículo
    Acceso abierto
    Measurement-Based Probabilistic Timing Analysis (MBPTA) has been shown to be an industrially viable method to estimate the Worst-Case Execution Time (WCET) of real-time programs running on processors including several ...
  • On the problem of evaluating the performance of multiprogrammed workloads 

    Cazorla, Francisco; Pajuelo González, Manuel Alejandro; Santana Jaria, Oliverio J.; Fernández Rodríguez, José Enrique; Valero Cortés, Mateo (2010-12)
    Artículo
    Acceso abierto
    Multithreaded architectures are becoming more and more popular. In order to evaluate their behavior, several methodologies and metrics have been proposed. A methodology defines when the measurements for a given workload ...
  • On the problem of minimizing workload execution time in SMT processors 

    Cazorla, Francisco; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernandez Garcia, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2007)
    Texto en actas de congreso
    Acceso abierto
    Most research work on (simultaneous multithreading processors) SMTs focuses on improving throughput and/or fairness, or on prioritizing some threads over others in a workload. In this paper, we discuss a new problem not ...
  • Per-task energy accounting in computing systems 

    Liu, Qixiao; Jiménez, Víctor; Moreto Planas, Miquel; Abella, Jaume; Cazorla, Francisco; Valero Cortés, Mateo (2013)
    Report de recerca
    Acceso abierto
    We present for the first time the concept of per-task energy accounting (PTEA) and relate it to per-task energy metering (PTEM). We show the benefits of supporting both in future computing systems. Using the shared last-level ...
  • Predictable performance in SMT processors: synergy between the OS and SMTs 

    Cazorla, Francisco; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernandez Prieto, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2006-07)
    Artículo
    Acceso abierto
    Current operating systems (OS) perceive the different contexts of simultaneous multithreaded (SMT) processors as multiple independent processing units, although, in reality, threads executed in these units compete for the ...
  • Probabilistic timing analysis on time-randomized platforms for the space domain 

    Fernandez, Mikel; Morales, David; Kosmidis, Leonidas; Bardizbanyan, Alen; Broster, Ian; Hernandez, Carles; Quiñones, Eduardo; Abella, Jaume; Cazorla, Francisco; Machado, Paulo; Fossati, Luca (Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
    Comunicación de congreso
    Acceso abierto
    Timing Verification is a fundamental step in real-time embedded systems, with measurement-based timing analysis (MBTA) being the most common approach used to that end. We present a Space case study on a real platform that ...
  • SEDEA: A sensible approach to account DRAM energy in multicore systems 

    Liu, Qixiao; Moreto Planas, Miquel; Abella, Jaume; Cazorla, Francisco; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Texto en actas de congreso
    Acceso abierto
    As the energy cost in todays computing systems keeps increasing, measuring the energy becomes crucial in many scenarios. For instance, due to the fact that the operational cost of datacenters largely depends on the energy ...