Now showing items 1-20 of 28

  • Adapting TDMA arbitration for measurement-based probabilistic timing analysis 

    Panic, Milos; Abella, Jaume; Quiñones, Eduardo; Hernandez, Carles; Ungerer, Theo; Cazorla, Francisco J. (Elsevier, 2017-07)
    Article
    Restricted access - publisher's policy
    Critical Real-Time Embedded Systems require functional and timing validation to prove that they will perform their functionalities correctly and in time. For timing validation, a bound to the Worst-Case Execution Time ...
  • Aging Assessment and Design Enhancement of Randomized Cache Memories 

    Trilla, David; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. (Institute of Electrical and Electronics Engineers (IEEE), 2017-01-17)
    Article
    Open Access
    Critical real-time systems require the estimation of the worst-case execution time (WCET) for scheduling purposes and resource budgeting. Measurement-based probabilistic timing analysis (MBPTA) has been shown recently as ...
  • Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis 

    Slijepcevic, Mladen; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. (IEEE, 2017-09-28)
    Conference lecture
    Open Access
    Wormhole-based NoCs (wNoCs) are widely accepted in high-performance domains as the most appropriate solution to interconnect an increasing number of cores in the chip. However, wNoCs suitability in the context of critical ...
  • Cache side-channel attacks and time-predictability in high-performance critical real-time systems 

    Trilla, David; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. (Association for Computing Machinery (ACM), 2018-06-24)
    Conference lecture
    Open Access
    Embedded computers control an increasing number of systems directly interacting with humans, while also manage more and more personal or sensitive information. As a result, both safety and security are becoming ubiquitous ...
  • Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration 

    Fernandez, Gabriel; Jalle, Javier; Abella, Jaume; Quiñones, Eduardo; Vardanega, Tullio; Cazorla, Francisco J. (Institute of Electrical and Electronics Engineers (IEEE), 2016-10-11)
    Article
    Open Access
    Numerous researchers have studied the contention that arises among tasks running in parallel on a multicore processor. Most of those studies seek to derive a tight and sound upper-bound for the worst-case delay with which ...
  • Design and implementation of a fair credit-based bandwidth sharing scheme for buses 

    Slijepcevic, Mladen; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. (Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
    Conference lecture
    Open Access
    Fair arbitration in the access to hardware shared resources is fundamental to obtain low worst-case execution time (WCET) estimates in the context of critical real-time systems, for which performance guarantees are essential. ...
  • Design and integration of hierarchical-placement multi-level caches for real-time systems 

    Benedicte, Pedro; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. (IEEE, 2018-04-23)
    Conference lecture
    Open Access
    Enabling timing analysis in the presence of caches has been pursued by the real-time embedded systems (RTES) community for years due to cache's huge potential to reduce software's worst-case execution time (WCET). However, ...
  • Dynamic software randomisation: Lessons learnec from an aerospace case study 

    Cros, Fabrice; Kosmidis, Leonidas; Wartel, Franck; Morales, David; Abella, Jaume; Broster, Ian; Cazorla, Francisco J. (2017-05-15)
    Conference lecture
    Open Access
    Timing Validation and Verification (V&V) is an important step in real-time system design, in which a system's timing behaviour is assessed via Worst Case Execution Time (WCET) estimation and scheduling analysis. For WCET ...
  • EPC Enacted: Integration in an Industrial Toolbox and Use against a Railway Application 

    Mezzetti, Enrico; Fernandez, Mikel; Bardizbanyan, Alen; Agirre, Irune; Abella, Jaume; Vardanega, Tullio; Cazorla, Francisco J. (Institute of Electrical and Electronics Engineers (IEEE), 2017-06-08)
    Conference lecture
    Open Access
    Measurement-based timing analysis approaches are increasingly making their way into several industrial domains on account of their good cost-benefit ratio. The trustworthiness of those methods, however, suffers from the ...
  • EPC: Extended Path Coverage for Measurement-Based Probabilistic Timing Analysis 

    Ziccardi, Marco; Mezzetti, Enrico; Vardanega, Tullio; Abella, Jaume; Cazorla, Francisco J. (IEEE, 2016-01-18)
    Conference lecture
    Open Access
    Measurement-based probabilistic timing analysis (MBPTA) computes trustworthy upper bounds to the execution time of software programs. MBPTA has the connotation, typical of measurement-based techniques, that the bounds ...
  • Execution time distributions in embedded safety-critical systems using extreme value theory 

    del Castillo, Joan; Padilla, Maria; Abella, Jaume; Cazorla, Francisco J. (Inderscience, 2017)
    Article
    Open Access
    Several techniques have been proposed to upper-bound the worst-case execution time behaviour of programs in the domain of critical real-time embedded systems. These computing systems have strong requirements regarding the ...
  • Fitting Software Execution-Time Exceedance into a Residual Random Fault in ISO-26262 

    Agirre, Irune; Cazorla, Francisco J.; Abella, Jaume; Hernandez, Carles; Mezzetti, Enrico; Azkarate-askasua, Mikel; Vardanega, Tullio (IEEE, 2018-09-01)
    Open Access
    Car manufacturers relentlessly replace or augment the functionality of mechanical subsystems with electronic components. Most such subsystems (e.g., steer-by-wire) are safety related, hence, subject to regulation. ISO-26262, ...
  • Increasing the Reliability of Software Timing Analysis for Cache-Based Processors 

    Milutinovic, Suzana; Mezzetti, Enrico; Abella, Jaume; Cazorla, Francisco J. (IEEE, 2019-06-01)
    Article
    Open Access
    Real-time systems are witnessing a significant increase in critical software's size, complexity, and performance needs, which can only be satisfied with high-performance hardware features. Cache memories, pervasively used ...
  • Industrial experiences with resource management under software randomization in ARINC653 avionics environments 

    Kosmidis, Leonidas; Maxim, Cristian; Jegu, Victor; Vatrinet, Francis; Cazorla, Francisco J. (Association for Computing Machinery (ACM), 2018-11-05)
    Conference lecture
    Open Access
    Injecting randomization in different layers of the computing platform has been shown beneficial for security, resilience to software bugs and timing analysis. In this paper, with focus on the latter, we show our experience ...
  • MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding 

    Díaz, Enrique; Fernández, Mikel; Kosmidis, Leonidas; Mezzetti, Enrico; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. (Springer International Publishing, 2017-05-30)
    Conference lecture
    Open Access
    In critical domains, reliable software execution is increasingly involving aspects related to the timing dimension. This is due to the advent of high-performance (complex) hardware, used to provide the rising levels of ...
  • Measurement-based cache representativeness on multipath programs 

    Milutinovic, Suzana; Abella, Jaume; Mezzetti, Enrico; Cazorla, Francisco J. (Association for Computing Machinery (ACM), 2018-06)
    Conference lecture
    Open Access
    Autonomous vehicles in embedded real-time systems increase critical-software size and complexity whose performance needs are covered with high-performance hardware features like caches, which however hampers obtaining WCET ...
  • Measurement-Based Worst-Case Execution Time Estimation Using the Coefficient of Variation 

    Abella, Jaume; Padilla, Maria; del Castillo, Joan; Cazorla, Francisco J. (Association for Computing Machinery (ACM), 2017-07)
    Article
    Open Access
    Extreme Value Theory (EVT) has been historically used in domains such as finance and hydrology to model worst-case events (e.g., major stock market incidences). EVT takes as input a sample of the distribution of the variable ...
  • Modelling bus contention during system early design stages 

    Trilla, David; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. (IEEE, 2017-07-31)
    Conference lecture
    Open Access
    Reliably upperbounding contention in multicore shared resources is of prominent importance in the early design phases of critical real-time systems to properly allocate time budgets to applications. However, during early ...
  • Modelling multicore contention on the AURIXTM TC27x 

    Díaz, Enrique; Mezzetti, Enrico; Kosmidis, Leonidas; Abella, Jaume; Cazorla, Francisco J. (Association for Computing Machinery (ACM), 2018-06-24)
    Conference lecture
    Open Access
    Multicores are becoming ubiquitous in automotive. Yet, the expected benefits on integration are challenged by multicore contention concerns on timing V&V. Worst-case execution time (WCET) estimates are required as early ...
  • On assessing the viability of probabilistic scheduling with dependent tasks 

    Abella, Jaume; Mezzetti, Enrico; Cazorla, Francisco J. (Association for Computing Machinery (ACM), 2019-04-08)
    Conference lecture
    Open Access
    Despite the significant interest, in the last years, in probabilistic scheduling and probabilistic timing analysis, the interrelation between them has been scarcely addressed. Probabilistic scheduling approaches typically ...