Browsing by Contributor "Casas Guix, Marc"

Now showing items 1-12 of 12

  • Adaptive and application dependant runtime guided hardware reconfiguration for the IBM POWER7 

    Prat Robles, David (Universitat Politècnica de Catalunya, 2014-09-04)
    Master thesis
    Open Access
    The aim of this project is to develop adaptive resource management systems for the im- provement of the power-performance metrics associated with the current and future IBM POWER-series microprocessors.

  • Exploiting asymmetric multi-core systems with flexible system software 

    Chronaki, Kallia (Universitat Politècnica de Catalunya, 2018-11-21)
    Doctoral thesis
    Open Access
    Asymmetric multi-cores (AMCs) are a successful architectural solution for both mobile devices and supercomputers. These architectures combine different types of processing cores designed at different performance and power ...

  • Exploiting task-based programming models for resilience 

    Jaulmes, Luc Etienne (Universitat Politècnica de Catalunya, 2019-06-21)
    Doctoral thesis
    Open Access
    Hardware errors become more common as silicon technologies shrink and become more vulnerable, especially in memory cells, which are the most exposed to errors. Permanent and intermittent faults are caused by manufacturing ...

  • Exploring Scalability Techniques of OmpSs 

    Brumar, Iulian Valentin (Universitat Politècnica de Catalunya, 2014-06-27)
    Master thesis (pre-Bologna period)
    Restricted access - confidentiality agreement

  • Graph partitioning for the reduction of data transfer in task-based programming models 

    Sánchez Barrera, Isaac (Universitat Politècnica de Catalunya, 2016-07)
    Master thesis
    Open Access
    Covenantee:  Barcelona Supercomputing Centre
    Current high performance computing architectures are composed of large shared memory NUMA nodes, among other components. Such nodes are becoming increasingly complex as they have several NUMA domains with different access ...

  • Parallelization techniques of the x264 video encoder 

    Ruiz Muñoz, Daniel (Universitat Politècnica de Catalunya, 2014-06-20)
    Master thesis (pre-Bologna period)
    Open Access
    [CASTELLÀ] Aquest projecte consisteix en portar el codificador de video x264 que es troba a la suite de benchmarks PARSEC utilitzant el model de promació OmpSs. Per fer això haurem d'avaluar el rendiment de les versions ...

  • Runtime assisted cache memory optimizations 

    Dimic, Vladimir (Universitat Politècnica de Catalunya, 2015-07-09)
    Master thesis
    Restricted access - confidentiality agreement

  • Simulation methodologies for future large-scale parallel systems 

    Grass, Thomas (Universitat Politècnica de Catalunya, 2017-10-09)
    Doctoral thesis
    Open Access
    Since the early 2000s, computer systems have seen a transition from single-core to multi-core systems. While single-core systems included only one processor core on a chip, current multi-core processors include up to tens ...

  • Tècniques de paral·lelització del simulador Facesim 

    Vidal Ortiz, Raul (Universitat Politècnica de Catalunya, 2015-01-26)
    Bachelor thesis
    Open Access
    [CASTELLÀ] Este proyecto hace una evaluación de OmpSs como tecnología para entornos de centros de datos en busca de mejoras en el mantenimiento de aplicaciones así como su eficiencia y costes. Facesim ha sido utilizada ...

  • Towards resource-aware computing for task-based runtimes and parallel architectures 

    Chasapis, Dimitrios (Universitat Politècnica de Catalunya, 2019-04-24)
    Doctoral thesis
    Open Access
    Current large scale systems show increasing power demands, to the point that it has become a huge strain on facilities and budgets. The increasing restrictions in terms of power consumption of High Performance Computing ...

  • Transparent management of scratchpad memories in shared memory programming models 

    Álvarez Martín, Lluc (Universitat Politècnica de Catalunya, 2015-12-16)
    Doctoral thesis
    Open Access
    Cache-coherent shared memory has traditionally been the favorite memory organization for chip multiprocessors thanks to its high programmability. In this organization the cache hierarchy is in charge of moving the data and ...

  • Vector architectures for Exascale 

    Caminal Pallarés, Helena (Universitat Politècnica de Catalunya, 2017-07-03)
    Master thesis
    Restricted access - confidentiality agreement