Browsing by Author "Cabo Pitarch, Guillem"
Now showing items 1-15 of 15
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An academic RISC-V silicon implementation based on open-source components
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Conference report
Open AccessThe design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V ... -
De-RISC: A complete RISC-V based space-grade platform
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Conference report
Open AccessThe H2020 EIC-FTI De-RISC project develops a RISC-V space-grade platform to jointly respond to several emerging, as well as longstanding needs in the space domain such as: (1) higher performance than that of monocore and ... -
De-RISC: the First RISC-V space-grade platform for safety-critical systems
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Conference report
Open AccessThe increasing needs for performance in the space domain for highly autonomous systems calls for more powerful space MPSoCs and appropriate hypervisors to master them. These platforms must adhere to strict reliability, ... -
DVINO: A RISC-V vector processor implemented in 65nm technology
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Conference lecture
Open AccessThis paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM ... -
End-to-end QoS for the open source safety-relevant RISC-V SELENE platform
(arXiv, 2022)
Conference report
Open AccessThis paper presents the end-to-end QoS approach to provide performance guarantees followed in the SELENEplatform, a high-performance RISC-V based heterogeneous SoC for safety-related real-time systems. Our QoS approach ... -
Hardware implementation of statistics units for multicores in safety-critical real-time systems
(Universitat Politècnica de Catalunya, 2020-10)
Master thesis
Restricted access - confidentiality agreement -
SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Conference report
Open AccessSafety-related systems, such as those in automotive, avionics and space, impose the existence of appropriate safety measures to meet the safety requirements of the system. In the case of the highest integrity level ... -
SafeDE: A low-cost hardware solution to enforce diverse redundancy in multicores
(Institute of Electrical and Electronics Engineers (IEEE), 2022-06)
Article
Open AccessFailure risk must be tiny in high-integrity systems, such as those in cars, satellites and aircraft. Hence, safety measures must be deployed to avoid a single fault leading to a failure. Redundancy has been often used to ... -
SafeDM: a hardware diversity monitor for redundant execution on non-lockstepped cores
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Conference report
Open AccessComputing systems in the safety domain, such as those in avionics or space, require specific safety measures related to the criticality of the deployment. A problem these systems face is that of transient failures in ... -
SafeSoftDR: A library to enable software-based diverse redundancy for safety-critical tasks
(arXiv, 2022)
Conference report
Open AccessApplications with safety requirements have become ubiquitous nowadays and can be found in edge devices of all kinds. However, microcontrollers in those devices, despite offering moderate performance by implementing multicores ... -
SafeSU-2: a safe statistics unit for space MPSoCs
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Conference report
Open AccessAdvanced statistics units (SUs) have been proven effective for the verification, validation and implementation of safety measures as part of safety-related MPSoCs. This is the case, for instance, of the RISC-V MPSoC by ... -
SafeSU: an extended statistics unit for multicore timing interference
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Conference report
Open AccessStatistics units (SUs) in MPSoCs are becoming increasingly used for the (1) verification and (2) validation of multicore timing interference, as well as for (3) deploying safety measures in safety-related real-time systems. ... -
SafeTI: a hardware traffic injector for MPSoC functional and timing validation
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Conference report
Open AccessFunctional and timing validation of safety-related MPSoCs requires testing specific traffic patterns in the on-chip interconnects. Generally, testing needs to be performed by using software tests whose degree of control ... -
SafeX: Open source hardware and software components for safety-critical systems
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Conference report
Open AccessRISC-V Instruction Set Architecture (ISA) emerges as an opportunity to develop open source hardware without being subject to expensive licenses or export restrictions. A plethora of initiatives are nowadays developing ... -
Unboxing the sand: on deploying safety measures in the programmable logic of COTS MPSoCs
(Association Aéronautique et Astronautique de France (3AF), 2022)
Conference report
Open AccessThe lack of sufficient hardware support for functional safety precludes the full adoption of many Commercial Off-the-Shelf (COTS) MPSoCs in safety-related systems, such as those in the aerospace industry. Some recent MPSoCs ...
