Now showing items 1-3 of 3

    • CAD directions for high performance asynchronous circuits 

      Stevens, Kenneth S.; Rotem, Shai; Burns, Steven M.; Cortadella, Jordi; Ginosar, Ran; Kishinevsky, Michael; Roncken, Marly (Association for Computing Machinery (ACM), 1999)
      Conference report
      Open Access
      This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using relative timing. This methodology was developed for a prototype iA32 ...
    • Lazy transition systems and asynchronous circuits synthesis with relative timing assumptions 

      Cortadella, Jordi; Kishinevsky, Michael; Burns, Steven M.; Kondratyev, Alex; Lavagno, Luciano; Stevens, Kenneth S.; Taubin, Alexander; Yakovlev, Alex (2002-02)
      Article
      Open Access
      This paper presents a design flow for timed asynchronous circuits. It introduces lazy transitions systems as a new computational model to represent the timing information required for synthesis. The notion of laziness ...
    • Synthesis of asynchronous control circuits with automatically generated relative timing assumptions 

      Cortadella, Jordi; Kishinevsky, Michael; Burns, Steven M.; Stevens, Kenneth S. (Institute of Electrical and Electronics Engineers (IEEE), 1999)
      Conference report
      Open Access
      This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ensure functionality. Relative timing assumptions ...