Browsing by Author "Boneti, Carlos"

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    • A dynamic scheduler for balancing HPC applications 

      Boneti, Carlos; Gioiosa, Roberto; Cazorla, Francisco; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
      Conference report
      Open Access
      Load imbalance cause significant performance degradation in High Performance Computing applications. In our previous work we showed that load imbalance can be alleviated by modern MT processors that provide mechanisms for ...

    • Balancing HPC applications through smart allocation of resources in MT processors 

      Boneti, Carlos; Gioiosa, Roberto; Cazorla, Francisco; Corbalán González, Julita; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
      Conference report
      Open Access
      Many studies have shown that load imbalancing causes significant performance degradation in High Performance Computing (HPC) applications. Nowadays, Multi-Threaded (MT1) processors are widely used in HPC for their good ...

    • Software-controlled priority characterization of POWER5 processor 

      Boneti, Carlos; Cazorla, Francisco; Gioiosa, Roberto; Buyuktosunoglu, Alper; Cher, Chen-Yong; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
      Conference report
      Open Access
      Due to the limitations of instruction-level parallelism, thread-level parallelism has become a popular way to improve processor performance. One example is the IBM POWER5TM processor, a two-context simultaneous-multithreaded ...