Now showing items 1-4 of 4

    • A memory model for RISC-V 

      Arvind (Barcelona Supercomputing Center, 2017-09-10)
      Conference report
      Open Access
      Historically memory models for multiprocessors have not been designed deliberately but have just emerged. Practically every microarchitectural optimization, which is transparent in a single threaded setting, becomes ...
    • Big data applications on flash storage with accelerators 

      Arvind (Barcelona Supercomputing Center, 2017-09-10)
      Open Access
      Fast content-based searches and complex analytics of the vast amount of data collected via social media, cell phones, ubiquitous smart sensors, and satellites is likely to be the biggest economic driver for the IT industry ...
    • MI6: secure enclaves in a speculative out-of-order processor 

      Arvind (Barcelona Supercomputing Center, 2020)
      Conference report
      Open Access
      MI6 is an aggressive, speculative out-of-order processor to support Secure Enclaves, which restore the process isolation guarantees broken by recent attacks exploiting microarchitectural sidechannels.Our threat model ...
    • Microarchitectural design-space exploration of an in-order RISC-V processor in a 22nm CMOS technology 

      Doblas Font, Max; Wright, Andrew; Sonmez, Nehir; Moreto Planas, Miquel; Arvind (European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), 2021)
      Conference lecture
      Open Access
      The purpose of this paper is to explore the trade-offs between IPC and maximum clock frequency in an in-order processor design. This work evaluates the impact on the performance and frequency of different pipeline ...