Now showing items 1-20 of 227

    • 2018 International Symposium on Computer Architecture influential paper award 

      González Colás, Antonio María (2018-07-01)
      Article
      Open Access
      The International Symposium on Computer Architecture (ISCA) recognizes every year the most influential paper published in this conference 15 years earlier, based on its impact on research, development, products or ideas. ...
    • A control and management architecture supporting autonomic NFV services 

      Velasco Esteban, Luis Domingo; Casellas Regi, Ramón; Llana, Sergio; Gifre Renom, Lluís; Martínez Rivera, Ricardo Victor; Vilata, Ricard; Muñoz González, Raul; Ruiz, Marc (2019-02)
      Article
      Open Access
      The proposed control, orchestration and management (COM) architecture is presented from a high-level point of view; it enables the dynamic provisioning of services such as network data connectivity or generic network slicing ...
    • A hardware accelerator for ORB-SLAM 

      Taranco, Raúl (Universitat Politècnica de Catalunya, 2019-10-17)
      Master thesis
      Open Access
      Simultaneous Localization And Mapping (SLAM) is a key component of self-driving cars. We study ORB-SLAM, a SLAM state-of-the-art solution, and develop a hardware accelerator for a critical part of it: ORB feature extraction. ...
    • A hybrid web server architecture for secure e-business web applications 

      Beltran Querol, Vicenç; Carrera Pérez, David; Guitart Fernández, Jordi; Torres Viñals, Jordi; Ayguadé Parra, Eduard (2005-09)
      Article
      Restricted access - publisher's policy
      Nowadays the success of many e-commerce applications, such as on-line banking, depends on their reliability, robustness and security. Designing a web server architecture that keeps these properties under high loads is a ...
    • A Multi-core processor for hard real-time systems 

      Paolieri, Marco (Universitat Politècnica de Catalunya, 2011-11-04)
      Doctoral thesis
      Open Access
      The increasing demand for new functionalities in current and future hard real-time embedded systems, like the ones deployed in automotive and avionics industries, is driving an increment in the performance required in ...
    • A self-adaptive hardware architecture with fault tolerance capabilities 

      Soto, Javier; Moreno Aróstegui, Juan Manuel; Cabestany Moncusí, Joan (2013-12-09)
      Article
      Restricted access - publisher's policy
      This paper describes a Fault Tolerance System (FTS) implemented in a new self-adaptive hardware architecture. This architecture is based on an array of cells that implements in a distributed way self-adaptive capabilities. ...
    • A two-dimensional architecture for end-to-end resource management in virtual network environments 

      Wang, Ning; Zhang, Yi; Serrat Fernández, Juan; Gorricho Moreno, Juan Luis; Guo, Tao; Hu, Zheng; Zhang, Ping (2012-09)
      Article
      Restricted access - publisher's policy
      In recent years, various network virtualization techniques have been proposed for flexibly supporting heterogeneous services over virtual network platforms. However, systematic views on how virtual network resources (VNRs) ...
    • Adaptación a un entorno J2EE desde un sistema centralizado Host 

      Ferré Vaquer, Maria Teresa (Universitat Politècnica de Catalunya, 2013-12-20)
      Master thesis (pre-Bologna period)
      Restricted access - author's decision
      Explain J2EE adaptation process, advantages, functional design, etc.
    • Adaptive fault-tolerant architecture for unreliable device technologies 

      Aymerich, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio (CRC Press, Taylor and Francis Group, 2013-06-03)
      Part of book or chapter of book
      Restricted access - publisher's policy
      Nanoelectronic Device Applications Handbook gives a comprehensive snapshot of the state of the art in nanodevices for nanoelectronics applications. Combining breadth and depth, the book includes 68 chapters on topics that ...
    • Adaptive memory hierarchies for next generation tiled microarchitectures 

      Herrero Abellanas, Enric (Universitat Politècnica de Catalunya, 2011-07-05)
      Doctoral thesis
      Open Access
      Les últimes dècades el rendiment dels processadors i de les memòries ha millorat a diferent ritme, limitant el rendiment dels processadors i creant el conegut memory gap. Sol·lucionar aquesta diferència de rendiment és un ...
    • Admission control for multi-tenant radio access networks 

      Pérez Romero, Jordi; Sallent Roig, José Oriol; Ferrús Ferré, Ramón Antonio; Agustí Comes, Ramon (2017)
      Conference report
      Restricted access - publisher's policy
      The sharing of Radio Access Networks is gaining momentum in small cell scenarios, due to the associated reduction in capital and operational costs. In this scenario, the split of radio resources among tenants sharing the ...
    • Algoritmos de ordenación conscientes de la arquitectura y las características de los datos 

      Jiménez González, Daniel (Universitat Politècnica de Catalunya, 2004-07-02)
      Doctoral thesis
      Open Access
      En esta tesis analizamos y presentamos algoritmos de ordenación secuencial y paralelo que explotan la jerarquía de memoria del computador usado y/o reducen la comunicación de los datos. Sin embargo, aunque los objetivos ...
    • An abstraction methodology for the evaluation of multi-core multi-threaded architectures 

      Zilan, Ruken; Verdú Mulà, Javier; García Vidal, Jorge; Nemirovsky, Mario; Milito, Rodolfo; Valero Cortés, Mateo (IEEE Computer Society Publications, 2011)
      Conference report
      Restricted access - publisher's policy
      As the evolution of multi-core multi-threaded processors continues, the complexity demanded to perform an extensive trade-off analysis, increases proportionally. Cycle-accurate or trace-driven simulators are too slow to ...
    • An Approach to a Fault Tolerance LISP Architecture 

      Martínez Manzanilla, Anny Gabriela; Ramírez, Wilson; Germán Duarte, Martín; Serral Gracià, René; Marín Tordera, Eva; Yannuzzi, Marcelo; Masip Bruin, Xavier (Springer Verlag, 2011)
      Conference report
      Open Access
      Next Generation Internet points out the challenge of addressing "things" on both a network with (wired) and without (wireless) infrastructure. In this scenario, new efficient and scalable addressing and routing schemes ...
    • An approximate analysis of synchronous multiple bus 

      González Peña, Luis Eduardo; Sanvicente Gargallo, Emilio (1985)
      External research report
      Open Access
      This paper presents an approximate analytic model for evaluating the performance of a loosely coupled multiprocessor architecture whose memory, organized in modules, is shared by all the processors. Each memory module (Mi) ...
    • An energy-efficient and scalable eDRAM-based register file architecture for GPGPU 

      Jing, Naifeng; Shen, Yao; Lu, Yao; Ganapathy, Shrikanth; Mao, Zhigang; Guo, Minyi; Canal Corretger, Ramon; Liang, Xiaoyao (ACM, 2013)
      Conference report
      Restricted access - publisher's policy
      The heavily-threaded data processing demands of streaming multiprocessors (SM) in a GPGPU require a large register file (RF). The fast increasing size of the RF makes the area cost and power consumption unaffordable for ...
    • An on-line test strategy and analysis for a 1T1R crossbar memory 

      Escudero, Manel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Vourkas, Ioannis (Institute of Electrical and Electronics Engineers (IEEE), 2017)
      Conference report
      Open Access
      Memristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable ...
    • Analysis and architectural support for parallel stateful packet processing 

      Verdú Mulà, Javier (Universitat Politècnica de Catalunya, 2008-07-09)
      Doctoral thesis
      Open Access
      The evolution of network services is closely related to the network technology trend. Originally network nodes forwarded packets from a source to a destination in the network by executing lightweight packet processing, or ...
    • Analysis and mitigation of writeback cache lock-ups in Linux 

      Méndez Orero, Alba (Universitat Politècnica de Catalunya, 2020-06)
      Bachelor thesis
      Open Access
      Linux caches disk I/O for performance: writes complete immediately from userspace perspective, and are committed to storage later. But in the presence of heavy writers, this buffering can easily hurt system responsiveness ...
    • Analysis and simulation of data prefetching algorithms for last-level cache memory 

      Escuín Blasco, Carlos (Universitat Politècnica de Catalunya, 2018-06-25)
      Master thesis
      Open Access
      Covenantee:   České vysoké učení technické v Praze
      Analysis and simulation of data prefetching algorithms for last-level cache memory. Analysis and comparison of one of the latest data prefetching algorithms in terms of performance, network utilization and prefetching accuracy.