• Adaptación a un entorno J2EE desde un sistema centralizado Host 

    Ferré Vaquer, Maria Teresa (Universitat Politècnica de Catalunya, 2013-12-20)
    Proyecto/Trabajo final de carrera
    Acceso restringido por decisión del autor
    Explain J2EE adaptation process, advantages, functional design, etc.
  • Adaptive fault-tolerant architecture for unreliable device technologies 

    Aymerich, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio (CRC Press, Taylor and Francis Group, 2013-06-03)
    Capítulo de libro
    Acceso restringido por política de la editorial
    Nanoelectronic Device Applications Handbook gives a comprehensive snapshot of the state of the art in nanodevices for nanoelectronics applications. Combining breadth and depth, the book includes 68 chapters on topics that ...
  • Admission control for multi-tenant radio access networks 

    Pérez Romero, Jordi; Sallent Roig, José Oriol; Ferrús Ferré, Ramón Antonio; Agustí Comes, Ramon (2017)
    Texto en actas de congreso
    Acceso restringido por política de la editorial
    The sharing of Radio Access Networks is gaining momentum in small cell scenarios, due to the associated reduction in capital and operational costs. In this scenario, the split of radio resources among tenants sharing the ...
  • A hybrid web server architecture for secure e-business web applications 

    Beltran Querol, Vicenç; Carrera Pérez, David; Guitart Fernández, Jordi; Torres Viñals, Jordi; Ayguadé Parra, Eduard (2005-09)
    Artículo
    Acceso restringido por política de la editorial
    Nowadays the success of many e-commerce applications, such as on-line banking, depends on their reliability, robustness and security. Designing a web server architecture that keeps these properties under high loads is a ...
  • An abstraction methodology for the evaluation of multi-core multi-threaded architectures 

    Zilan, Ruken; Verdú Mulà, Javier; García Vidal, Jorge; Nemirovsky, Mario; Milito, Rodolfo; Valero Cortés, Mateo (IEEE Computer Society Publications, 2011)
    Texto en actas de congreso
    Acceso restringido por política de la editorial
    As the evolution of multi-core multi-threaded processors continues, the complexity demanded to perform an extensive trade-off analysis, increases proportionally. Cycle-accurate or trace-driven simulators are too slow to ...
  • Analysis of CPI variance for dynamic binary translators/optimizers modules 

    Brankovic, Aleksandar; Stavrou, Kyriakos; Gibert Codina, Enric; González Colás, Antonio María (IEEE, 2012)
    Texto en actas de congreso
    Acceso restringido por política de la editorial
    Dynamic Binary Translators and Optimizers (DBTOs) have been established as a hot research topic. They are used in many different systems, such as emulation, instrumentation tools and innovative HW/SW co-designed ...
  • Analysis of NFV service design and management processes using ITIL and eTOM best practices 

    Nnabugwu, Samuel Nwadilobi (Universitat Politècnica de Catalunya, 2017-10-11)
    Projecte Final de Màster Oficial
    Acceso abierto
    The objective of this project is to analyse the design and process management of NFV and its operations using two of the most widely used and accepted best practices in telecommunication and IT industries. Focusing majorly ...
  • An Approach to a Fault Tolerance LISP Architecture 

    Martínez Manzanilla, Anny Gabriela; Ramírez, Wilson; Germán Duarte, Martín; Serral Gracià, René; Marín Tordera, Eva; Yannuzzi, Marcelo; Masip Bruin, Xavier (Springer Verlag, 2011)
    Texto en actas de congreso
    Acceso abierto
    Next Generation Internet points out the challenge of addressing "things" on both a network with (wired) and without (wireless) infrastructure. In this scenario, new efficient and scalable addressing and routing schemes ...
  • An approximate analysis of synchronous multiple bus 

    González Peña, Luis Eduardo; Sanvicente Gargallo, Emilio (1985)
    Report de recerca
    Acceso abierto
    This paper presents an approximate analytic model for evaluating the performance of a loosely coupled multiprocessor architecture whose memory, organized in modules, is shared by all the processors. Each memory module (Mi) ...
  • An energy-efficient and scalable eDRAM-based register file architecture for GPGPU 

    Jing, Naifeng; Shen, Yao; Lu, Yao; Ganapathy, Shrikanth; Mao, Zhigang; Guo, Minyi; Canal Corretger, Ramon; Liang, Xiaoyao (ACM, 2013)
    Texto en actas de congreso
    Acceso restringido por política de la editorial
    The heavily-threaded data processing demands of streaming multiprocessors (SM) in a GPGPU require a large register file (RF). The fast increasing size of the RF makes the area cost and power consumption unaffordable for ...
  • An on-line test strategy and analysis for a 1T1R crossbar memory 

    Escudero, Manel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Vourkas, Ioannis (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Texto en actas de congreso
    Acceso abierto
    Memristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable ...
  • Approaches for Task Affinity in OpenMP 

    Terboven, Christian; Hahnfeld, Jonas; Teruel, Xavier; Mateo, Sergi; Duran, Alejandro; Klemm, Michael; Olivier, Stephen L.; Supinski, Bronis R. (Springer International Publishing, 2016-09-21)
    Comunicación de congreso
    Acceso abierto
    OpenMP tasking supports parallelization of irregular algorithms. Recent OpenMP specifications extended tasking to increase functionality and to support optimizations, for instance with the taskloop construct. However, task ...
  • Approximate task memoization 

    Brumar, Iulian Valentin (Universitat Politècnica de Catalunya, 2016-10)
    Projecte Final de Màster Oficial
    Acceso restringido por acuerdo de confidencialidad
  • Architecture of a specialized back-end high performance computing-based PCE for flexgrid networks 

    Gifre Renom, Lluís; Velasco Esteban, Luis Domingo; Navarro, Nacho (Institute of Electrical and Electronics Engineers (IEEE), 2013)
    Texto en actas de congreso
    Acceso restringido por política de la editorial
    The requirement of executing network re-optimization operations to efficiently manage and deploy new generation flexgrid-based optical networks has brought to light the need of some specialized PCEs capable of performing ...
  • A self-adaptive hardware architecture with fault tolerance capabilities 

    Soto, Javier; Moreno Aróstegui, Juan Manuel; Cabestany Moncusí, Joan (2013-12-09)
    Artículo
    Acceso restringido por política de la editorial
    This paper describes a Fault Tolerance System (FTS) implemented in a new self-adaptive hardware architecture. This architecture is based on an array of cells that implements in a distributed way self-adaptive capabilities. ...
  • A two-dimensional architecture for end-to-end resource management in virtual network environments 

    Wang, Ning; Zhang, Yi; Serrat Fernández, Juan; Gorricho Moreno, Juan Luis; Guo, Tao; Hu, Zheng; Zhang, Ping (2012-09)
    Artículo
    Acceso restringido por política de la editorial
    In recent years, various network virtualization techniques have been proposed for flexibly supporting heterogeneous services over virtual network platforms. However, systematic views on how virtual network resources (VNRs) ...
  • Automatic generation and testing of application specific hardware accelerators on a new reconfigurable OpenSPARC platform 

    González Álvarez, Cecilia; Fernández, Mikel; Jiménez González, Daniel; Álvarez Martínez, Carlos; Martorell Bofill, Xavier (2011)
    Texto en actas de congreso
    Acceso abierto
    Specific hardware customization for scientific applications has shown a big potential to address the current holy grail in computer architecture: reducing power consumption while increasing performance. In particular, the ...
  • Automatic refinement of parallel applications structure detection 

    González, Juan; Huck, Kevin; Giménez Lucas, Judit; Labarta Mancho, Jesús José (2012)
    Texto en actas de congreso
    Acceso restringido por política de la editorial
    Analyzing parallel programs has become increasingly difficult due to the immense amount of information collected on large systems. In this scenario, cluster analysis has been proved to be a useful technique to reduce the ...
  • Avaluació de la generació de serveis de xarxa en escenaris híbrids basats en SDN, NFV i SFC 

    Fernandez Ribas, Rosa (Universitat Politècnica de Catalunya, 2017-10-26)
    Trabajo final de grado
    Acceso abierto
    Currently, we are experiencing the era of digitization that is suffering challenges due to the fast growth in demand of bandwidth and services innovations which are leading to traditional networks at its limit. This situation ...
  • Buffer sizing for self-timed stream programs on heterogeneous distributed memory multiprocessors 

    Carpenter, Paul; Ramírez Bellido, Alejandro; Ayguadé Parra, Eduard (Springer Verlag, 2010)
    Texto en actas de congreso
    Acceso restringido por política de la editorial
    Stream programming is a promising way to expose concurrency to the compiler. A stream program is built from kernels that communicate only via point-to-point streams. The stream compiler statically allocates these kernels ...