Browsing by Author "Armejach, Adrià"

Now showing items 1-6 of 6

    • An empirical evaluation of High-Level Synthesis languages and tools for database acceleration 

      Arcas Abella, Oriol; Ndu, Geoffrey; Sönmez, Nehir; Ghasempour, Mohsen; Armejach, Adrià; Navaridas, Javier; Song, Wei; Mawer, John; Cristal Kestelman, Adrián; Lujan, Mikel (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Conference report
      Open Access
      High Level Synthesis (HLS) languages and tools are emerging as the most promising technique to make FPGAs more accessible to software developers. Nevertheless, picking the most suitable HLS for a certain class of algorithms ...

    • Circuit design of a dual-versioning L1 data cache for optimistic concurrency 

      Seyedi, Azam; Armejach, Adrià; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Hur, Ibrahim; Valero Cortés, Mateo (2011)
      Research report
      Open Access
      This paper proposes a novel L1 data cache design with dual-versioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this new cache architecture, each dvSRAM cell ...

    • Commit on overflow 

      Stipic, Srdjan; Armejach, Adrià; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2014)
      Research report
      Open Access
      Current commercial CPUs have hardware support for speculative lock elision (SLE). SLE tries to elide the lock by speculatively executing lock protected critical section. If the speculation fails, SLE acquires the lock and ...

    • Design Space Exploration of Next-Generation HPC Machines 

      Gómez, Constantino; Martínez, Francesc; Armejach, Adrià; Moretó, Miquel; Mantovani, Filippo; Casas, Marc (2019)
      Research report
      Open Access
      The landscape of High Performance Computing (HPC) system architectures keeps expanding with new technologies and increased complexity. With the goal of improving the efficiency of next-generation large HPC systems, ...

    • Efficient Direct Convolution Using Long SIMD Instructions 

      Santana, Alexandre de Limas; Armejach, Adrià; Casas, Marc (Association for Computing Machinery (ACM), 2023)
      Conference lecture
      Open Access
      This paper demonstrates that state-of-the-art proposals to compute convolutions on architectures with CPUs supporting SIMD instructions deliver poor performance for long SIMD lengths due to frequent cache conflict misses. ...

    • MUSA: a multi-level simulation approach for next-generation HPC machines 

      Grass, Thomas; Allande, César; Armejach, Adrià; Rico, Alejandro; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo; Casas, Marc; Moreto Planas, Miquel (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference report
      Restricted access - publisher's policy
      The complexity of High Performance Computing (HPC) systems is increasing in the number of components and their heterogeneity. Interactions between software and hardware involve many different aspects which are typically ...