Now showing items 1-5 of 5

    • Contention-aware performance monitoring counter support for real-time MPSoCs 

      Jalle Ibarra, Javier; Fernández, Mikel; Abella Ferrer, Jaume; Andersson, Jan; Patte, Mathieu; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference lecture
      Open Access
      Tasks running in MPSoCs experience contention delays when accessing MPSoC’s shared resources, complicating task timing analysis and deriving execution time bounds. Understanding the Actual Contention Delay (ACD) each task ...
    • De-RISC – Dependable Real-Time Infrastructure for Safety-Critical Computer Systems 

      Gómez, Francisco; Masmano, Miguel; Nicolau, Vicente; Andersson, Jan; Le Rhun, Jimmy; Trilla, David; Gallego, Felipe; Cabo, Guillem; Abella Ferrer, Jaume (Ada-Europe, 2020-06)
      Article
      Open Access
      The space domain demands increased performance, reliable and easy to verify and validate platforms tomatch the requirements of highly autonomous missions and systems that need to undergo qualification and certification ...
    • De-RISC: the First RISC-V space-grade platform for safety-critical systems 

      Wessman, Nils-Johan; Malatesta, Fabio; Andersson, Jan; Gómez Molinero, Paco; Masmano Tello, Miguel; Nicolau Gallego, Vicente; Le Rhun, Jimmy; Cabo Pitarch, Guillem; Bas Jalón, Francisco; Lorenzo Ortega, Rubén; Sala Sucarrats, Oriol; Trilla Rodríguez, David; Abella Ferrer, Jaume (Institute of Electrical and Electronics Engineers (IEEE), 2021)
      Conference report
      Open Access
      The increasing needs for performance in the space domain for highly autonomous systems calls for more powerful space MPSoCs and appropriate hypervisors to master them. These platforms must adhere to strict reliability, ...
    • PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis 

      Cazorla, Francisco J.; Abella Ferrer, Jaume; Andersson, Jan; Vardanega, Tullio; Vatrinet, Francis; Bate, Iain; Broster, Ian; Azkarate-askasua, Mikel; Wartel, Franck; Cucu, Liliana; Cros, Fabrice; Farrall, Glenn; Gogonel, Adriana; Gianarro, Andrea; Triquet, Benoit; Hernandez, Carles; Lo, Code; Maxim, Cristian; Morales, David; Quiñones, Eduardo; Mezzetti, Enrico; Kosmidis, Leonidas; Aguirre, Irune; Fernandez, Mikel; Slijepcevic, Mladen; Conmy, Philippa; Talaboulma, Walid (IEEE, 2016-08-31)
      Conference lecture
      Open Access
      The use of increasingly complex hardware and software platforms in response to the ever rising performance demands of modern real-time systems complicates the verification and validation of their timing behaviour, which ...
    • Random Modulo: A new processor cache design for real-time critical systems 

      Hernández, Carles; Abella Ferrer, Jaume; Gianarro, Andrea; Andersson, Jan; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference lecture
      Open Access
      Cache memories have a huge impact on software's worst-case execution time (WCET). While enabling the seamless use of caches is key to provide the increasing levels of (guaranteed) performance required by automotive software, ...