Browsing by Author "Andersson, Jan"
Now showing items 1-6 of 6
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Contention-aware performance monitoring counter support for real-time MPSoCs
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference lecture
Open AccessTasks running in MPSoCs experience contention delays when accessing MPSoC’s shared resources, complicating task timing analysis and deriving execution time bounds. Understanding the Actual Contention Delay (ACD) each task ... -
De-RISC – Dependable Real-Time Infrastructure for Safety-Critical Computer Systems
(Ada-Europe, 2020-06)
Article
Open AccessThe space domain demands increased performance, reliable and easy to verify and validate platforms tomatch the requirements of highly autonomous missions and systems that need to undergo qualification and certification ... -
De-RISC: A complete RISC-V based space-grade platform
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Conference report
Open AccessThe H2020 EIC-FTI De-RISC project develops a RISC-V space-grade platform to jointly respond to several emerging, as well as longstanding needs in the space domain such as: (1) higher performance than that of monocore and ... -
De-RISC: the First RISC-V space-grade platform for safety-critical systems
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Conference report
Open AccessThe increasing needs for performance in the space domain for highly autonomous systems calls for more powerful space MPSoCs and appropriate hypervisors to master them. These platforms must adhere to strict reliability, ... -
PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis
(IEEE, 2016-08-31)
Conference lecture
Open AccessThe use of increasingly complex hardware and software platforms in response to the ever rising performance demands of modern real-time systems complicates the verification and validation of their timing behaviour, which ... -
Random Modulo: A new processor cache design for real-time critical systems
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference lecture
Open AccessCache memories have a huge impact on software's worst-case execution time (WCET). While enabling the seamless use of caches is key to provide the increasing levels of (guaranteed) performance required by automotive software, ...
