Now showing items 1-7 of 7

  • A fault-tolerant last level cache for CMPs operating at ultra-low voltage 

    Ferrerón, Alexandra; Alastruey, Jesús; Suárez Gracía, Dario; Monreal Arnal, Teresa; Ibáñez Marín, Pablo Enrique; Viñals Yúfera, Víctor (Elsevier, 2019-03)
    Article
    Restricted access - publisher's policy
    Voltage scaling to values near the threshold voltage is a promising technique to hold off the many-core power wall. However, as voltage decreases, some SRAM cells are unable to operate reliably and show a behavior consistent ...
  • Block disabling characterization and improvements in CMPs operating at ultra-low voltages 

    Ferrerón, Alexandra; Suárez Gracia, Darío; Alastruey, Jesús; Monreal Arnal, Teresa; Viñals Yufera, Víctor (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
    Open Access
    Power density has become the limiting factor in technology scaling as power budget restricts the amount of hardware that can be active at the same time. Reducing supply voltage to ultra-low voltage ranges close to the ...
  • Concertina: Squeezing in cache content to operate at near-threshold voltage 

    Ferrerón, Alexandra; Suárez Gracia, Darío; Alastruey, Jesús; Monreal Arnal, Teresa; Ibáñez, Pablo (2016-03-01)
    Article
    Open Access
    Scaling supply voltage to values near the threshold voltage allows a dramatic decrease in the power consumption of processors; however, the lower the voltage, the higher the sensitivity to process variation, and, hence, ...
  • Gestión de contenidos en caches operando a bajo voltaje 

    Ferrerón, Alexandra; Alastruey, Jesús; Suárez Gracía, Dario; Monreal Arnal, Teresa; Ibáñez Marín, Pablo Enrique; Viñals Yúfera, Víctor (2016)
    Conference report
    Open Access
    La eficiencia energética de las caches en chip puede mejorarse reduciendo su voltaje de alimentación (Vdd ). Sin embargo, este escalado de Vdd está limitado a una tensión Vddmin por debajo de la cual algunas celdas SRAM ...
  • Microarchitectural support for speculative register renaming 

    Alastruey, Jesús; Monreal Arnal, Teresa; Viñals Yufera, Víctor; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2007)
    Conference report
    Open Access
    This paper proposes and evaluates a new microarchitecture for out-of-order processors that supports speculative renaming. We call speculative renaming to the speculative omission of physical register allocation along with ...
  • Selección del tamaño del banco de registros y de la política de asignación de recursos en procesadores SMT 

    Alastruey, Jesús; Monreal Arnal, Teresa; Cazorla Almeida, Francisco Javier; Viñals Yúfera, Víctor; Valero Cortés, Mateo (Thomson Editores Spain, 2007)
    Conference report
    Open Access
    Este trabajo estudia el impacto del tamaño del banco de registros físico (BRF) en el rendimiento de procesadores Simultaneous Multithreading (SMT). Como es bien conocido, el BRF es un componente crítico en este tipo de ...
  • Selection of the register file size and the resource policy on SMT processors 

    Alastruey, Jesús; Monreal Arnal, Teresa; Cazorla Almeida, Francisco Javier; Viñals Yufera, Víctor; Valero Cortés, Mateo (IEEE Computer Society, 2008)
    Conference lecture
    Open Access
    The performance impact of the Physical Register File (PRF) size on Simultaneous Multithreading processors has not been extensively studied in spite of being a critical shared resource. In this paper we analyze the effect ...