Now showing items 1-20 of 52

  • Accurate ILP-Based Contention Modeling on Statically Scheduled Multicore Systems 

    Palomo, Xavier; Mezzetti, Enrico; Abella, Jaume; Bril, Reinder J.; Cazorla, Francisco J. (IEEE, 2019-06-24)
    Conference lecture
    Open Access
    Commercially available Off The Shelf (COTS) multicores have been assessed as the baseline computing platform even in the most conservative real-time domains. Multicore contention arising on shared hardware resources, with ...
  • Adapting TDMA arbitration for measurement-based probabilistic timing analysis 

    Panic, Milos; Abella, Jaume; Quiñones, Eduardo; Hernandez, Carles; Ungerer, Theo; Cazorla, Francisco J. (Elsevier, 2017-07)
    Article
    Open Access
    Critical Real-Time Embedded Systems require functional and timing validation to prove that they will perform their functionalities correctly and in time. For timing validation, a bound to the Worst-Case Execution Time ...
  • A detailed methodology to compute soft error rates in advanced technologies 

    Riera Villanueva, Marc; Canal Corretger, Ramon; Abella, Jaume; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Restricted access - publisher's policy
    System reliability has become a key design aspect for computer systems due to the aggressive technology miniaturization. Errors are typically dominated by transient faults due to radiation and are strongly related to the ...
  • Aging Assessment and Design Enhancement of Randomized Cache Memories 

    Trilla, David; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. (Institute of Electrical and Electronics Engineers (IEEE), 2017-01-17)
    Article
    Open Access
    Critical real-time systems require the estimation of the worst-case execution time (WCET) for scheduling purposes and resource budgeting. Measurement-based probabilistic timing analysis (MBPTA) has been shown recently as ...
  • Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification 

    Espinosa, Jaime; Hernandez, Carles; Abella, Jaume; de Andres, David; Ruiz, Juan C. (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Conference report
    Open Access
    Increasingly complex microcontroller designs for safety-relevant automotive systems require the adoption of new methods and tools to enable a cost-effective verification of their robustness. In particular, costs associated ...
  • Assessing the Adherence of an Industrial Autonomous Driving Framework to ISO 26262 Software Guidelines 

    Tabani, Hamid; Kosmidis, Leonidas; Abella, Jaume; Cazorla, Francisco J.; Bernat, Guillem (Association for Computing Machinery (ACM), 2019-06-06)
    Conference lecture
    Open Access
    The complexity and size of Autonomous Driving (AD) software are comparably higher than that of software implementing other (standard) functionalities in the car. To make things worse, a big fraction of AD software is not ...
  • AURIX TC277 Multicore Contention Model Integration for Automotive Applications 

    Mezzetti, Enrico; Barbina, Luca; Abella, Jaume; Botta, Stefania; Cazorla, Francisco J. (IEEE, 2019-05-16)
    Conference lecture
    Open Access
    The ability to produce early guaranteed performance (worst-case execution time) estimates for multicores, i.e. before software from different providers gets integrated onto the same critical system, is pivotal. This helps ...
  • Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis 

    Slijepcevic, Mladen; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. (IEEE, 2017-09-28)
    Conference lecture
    Open Access
    Wormhole-based NoCs (wNoCs) are widely accepted in high-performance domains as the most appropriate solution to interconnect an increasing number of cores in the chip. However, wNoCs suitability in the context of critical ...
  • Cache side-channel attacks and time-predictability in high-performance critical real-time systems 

    Trilla, David; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. (Association for Computing Machinery (ACM), 2018-06-24)
    Conference lecture
    Open Access
    Embedded computers control an increasing number of systems directly interacting with humans, while also manage more and more personal or sensitive information. As a result, both safety and security are becoming ubiquitous ...
  • Characterizing fault propagation in safety-critical processor designs 

    Espinosa, Jaime; Hernandez, Carles; Abella, Jaume (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Conference report
    Open Access
    Achieving reduced time-to-market in modern electronic designs targeting safety critical applications is becoming very challenging, as these designs need to go through a certification step that introduces a non-negligible ...
  • Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration 

    Fernandez, Gabriel; Jalle, Javier; Abella, Jaume; Quiñones, Eduardo; Vardanega, Tullio; Cazorla, Francisco J. (Institute of Electrical and Electronics Engineers (IEEE), 2016-10-11)
    Article
    Open Access
    Numerous researchers have studied the contention that arises among tasks running in parallel on a multicore processor. Most of those studies seek to derive a tight and sound upper-bound for the worst-case delay with which ...
  • Contention-aware performance monitoring counter support for real-time MPSoCs 

    Jalle Ibarra, Javier; Fernández, Mikel; Abella, Jaume; Andersson, Jan; Patte, Mathieu; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference lecture
    Open Access
    Tasks running in MPSoCs experience contention delays when accessing MPSoC’s shared resources, complicating task timing analysis and deriving execution time bounds. Understanding the Actual Contention Delay (ACD) each task ...
  • Data bus slicing for contention-free multicore real-time memory systems 

    Jalle Ibarra, Javier; Quiñones, Eduardo; Abella, Jaume; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Open Access
    Memory access contention is one of the main contributors to tasks' execution time variability in real-Time multicores. Existing techniques to control memory contention based on time-sharing memory access do not scale well ...
  • Design and implementation of a fair credit-based bandwidth sharing scheme for buses 

    Slijepcevic, Mladen; Hernandez, Carles; Abella, Jaume; Cazorla, Francisco J. (Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
    Conference lecture
    Open Access
    Fair arbitration in the access to hardware shared resources is fundamental to obtain low worst-case execution time (WCET) estimates in the context of critical real-time systems, for which performance guarantees are essential. ...
  • DIMP: A low-cost diversity metric based on circuit path analysis 

    Alcaide, Sergi; Hernandez, Carles; Roca, Antoni; Abella, Jaume (2017)
    Conference report
    Diversity has been regarded as a desirable property of redundant instances, since it allows circuits to behave differently in front of a given fault. However, while qualitatively diversity is a well-understood concept, ...
  • DReAM: An approach to estimate per-Task DRAM energy in multicore systems 

    Liu, Qixiao; Moreto Planas, Miquel; Abella, Jaume; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (2016-12)
    Article
    Open Access
    Accurate per-task energy estimation in multicore systems would allow performing per-task energy-aware task scheduling and energy-aware billing in data centers, among other applications. Per-task energy estimation is ...
  • Dynamic software randomisation: Lessons learnec from an aerospace case study 

    Cros, Fabrice; Kosmidis, Leonidas; Wartel, Franck; Morales, David; Abella, Jaume; Broster, Ian; Cazorla, Francisco J. (2017-05-15)
    Conference lecture
    Open Access
    Timing Validation and Verification (V&V) is an important step in real-time system design, in which a system's timing behaviour is assessed via Worst Case Execution Time (WCET) estimation and scheduling analysis. For WCET ...
  • ePAPI: Performance Application ProgrammingInterface for Embedded Platforms 

    Giesen, Jeremy; Mezzetti, Enrico; Abella, Jaume; Fernández, Enrique; Cazorla, Francisco J. (2019)
    Conference lecture
    Open Access
    Performance Monitoring Counters (PMCs) have been traditionally used in the mainstream computing domain to perform debugging and optimization of software performance. PMCs are increasingly considered in embedded time-critical ...
  • EPC Enacted: Integration in an Industrial Toolbox and Use against a Railway Application 

    Mezzetti, Enrico; Fernandez, Mikel; Bardizbanyan, Alen; Agirre, Irune; Abella, Jaume; Vardanega, Tullio; Cazorla, Francisco J. (Institute of Electrical and Electronics Engineers (IEEE), 2017-06-08)
    Conference lecture
    Open Access
    Measurement-based timing analysis approaches are increasingly making their way into several industrial domains on account of their good cost-benefit ratio. The trustworthiness of those methods, however, suffers from the ...
  • EPC: Extended Path Coverage for Measurement-Based Probabilistic Timing Analysis 

    Ziccardi, Marco; Mezzetti, Enrico; Vardanega, Tullio; Abella, Jaume; Cazorla, Francisco J. (IEEE, 2016-01-18)
    Conference lecture
    Open Access
    Measurement-based probabilistic timing analysis (MBPTA) computes trustworthy upper bounds to the execution time of software programs. MBPTA has the connotation, typical of measurement-based techniques, that the bounds ...