Exploració per tema "Predictable performance"

Ara es mostren els items 1-2 de 2

    • APPLE: Adaptive performance-predictable low-energy caches for reliable hybrid voltage operation 

      Maric, Bojan; Abella Ferrer, Jaume; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2013)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Semiconductor technology evolution enables the design of resource-constrained battery-powered ultra-low-cost chips required for new market segments such as environment, urban life and body monitoring. Caches have been shown ...

    • Architectural support for real-time task scheduling in SMT processors 

      Cazorla Almeida, Francisco Javier; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernández, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2005)
      Report de recerca
      Accés obert
      In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architectures suitable for use in embedded systems. ...