Exploració per tema "Multi-level cache"

Ara es mostren els items 1-2 de 2

    • HWP: hardware support to reconcile cache energy, complexity, performance and WCET estimates in multicore real-time systems 

      Benedicte Illescas, Pedro; Hernandez, C.; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2018)
      Text en actes de congrés
      Accés obert
      High-performance processors have deployed multilevel cache (MLC) systems for decades. In the embedded real-time market, the use of MLC is also on the rise, with processors for future systems in space, railway, avionics and ...

    • RPR: a random replacement policy with limited pathological replacements 

      Benedicte Illescas, Pedro; Hernández Luz, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2018)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Measurement-Based Probabilistic Timing Analysis (MBPTA) has consolidated as a technique to estimate probabilistic Worst-Case Execution Times (WCET) for critical software running on processors with high-performance hardware ...