Exploració per tema "Instruction-level parallelism"
Ara es mostren els items 1-3 de 3
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A case for resource-conscious out-of-order processors
(2003-12)
Article
Accés obertModern out-of-order processors tolerate long-latency memory operations by supporting a large number of in-flight instructions. This is achieved in part through proper sizing of critical resources, such as register files ... -
Improving latency tolerance of multithreading through decoupling
(2001-10)
Article
Accés obertThe increasing hardware complexity of dynamically scheduled superscalar processors may compromise the scalability of this organization to make an efficient use of future increases in transistor budget. SMT processors, ... -
Mirs: modulo scheduling with integrated register spilling
(2003-01)
Article
Accés restringit per política de l'editorialThe overlapping of loop iterations in software pipelining techniques imposes high register requirements. The schedule for a loop is valid if it requires at most the number of registers available in the target architecture. ...