• A case for resource-conscious out-of-order processors 

      Cristal Kestelman, Adrián; Martínez, José F; Llosa Espuny, José Francisco; Valero Cortés, Mateo (2003-12)
      Article
      Accés obert
      Modern out-of-order processors tolerate long-latency memory operations by supporting a large number of in-flight instructions. This is achieved in part through proper sizing of critical resources, such as register files ...
    • Improving latency tolerance of multithreading through decoupling 

      Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (2001-10)
      Article
      Accés obert
      The increasing hardware complexity of dynamically scheduled superscalar processors may compromise the scalability of this organization to make an efficient use of future increases in transistor budget. SMT processors, ...
    • Mirs: modulo scheduling with integrated register spilling 

      Zalamea León, Francisco Javier; Llosa Espuny, José Francisco; Ayguadé Parra, Eduard; Valero Cortés, Mateo (2003-01)
      Article
      Accés restringit per política de l'editorial
      The overlapping of loop iterations in software pipelining techniques imposes high register requirements. The schedule for a loop is valid if it requires at most the number of registers available in the target architecture. ...