Exploració per tema "EDGE architecture"
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Dynamic-vector execution on a general purpose EDGE chip multiprocessor
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
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Accés restringit per política de l'editorialThis paper proposes a cost-effective technique that morphs the available cores of a low power chip multiprocessor (CMP) into an accelerator for data parallel (DLP) workloads. Instead of adding a special-purpose vector ...