Exploració per tema "FPGA"
Ara es mostren els items 1-20 de 200
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3D vehicle detection on an FPGA from LiDAR point clouds
(Association for Computing Machinery (ACM), 2019)
Text en actes de congrés
Accés obertIn this paper is presented a deep neural network architecture designed to run on a field-programmable gate array (FPGA) for detection vehicle on LIDAR point clouds. This works present a network based on VoxelNet adapted ... -
A hardware runtime for task-based programming models
(2019-09-01)
Article
Accés obertTask-based programming models such as OpenMP 5.0 and OmpSs are simple to use and powerful enough to exploit task parallelism of applications over multicore, manycore and heterogeneous systems. However, their software-only ... -
A hardware/software co-design of K-mer counting using a CAPI-enabled FPGA
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertAdvances in Next Generation Sequencing (NGS) technologies have caused the proliferation of genomic applications to detect DNA mutations and guide personalized medicine. These applications have an enormous computational ... -
A highly parameterizable framework for Conditional Restricted Boltzmann Machine based workloads accelerated with FPGAs and OpenCL
(Elsevier, 2020-03-01)
Article
Accés obertConditional Restricted Boltzmann Machine (CRBM) is a promising candidate for a multidimensional system modeling that can learn a probability distribution over a set of data. It is a specific type of an artificial neural ... -
A large-scale spiking neural networks emulation architecture
(Universitat Politècnica de Catalunya, 2014-09-09)
Projecte Final de Màster Oficial
Accés obertThe purpose of this work is to design a new version (called SNAVA+) of the architecture SNAVA, an SNN hardware emulator implemented on a XilinX Kintex-7 FPGA. SNAVA+ increases the capabilities of SNAVA in order to have a ... -
A new beam synchronous processing architecture with a fixed frequency processing clock: application to transient beam loading compensation in the CERN SPS machine
(2021-02-01)
Article
Accés obertNew projects being implemented or planned at CERN, such as the LHC Injectors Upgrade (LIU), the High-Luminosity LHC (HL-LHC) or the Future Circular Collider (FCC), motivate the change of several architectural paradigms in ... -
A novel FPGA-based high throughput accelerator for binary search trees
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés obertThis paper presents a deeply pipelined and massively parallel Binary Search Tree (BST) accelerator for Field Programmable Gate Arrays (FPGAs). Our design relies on the extremely parallel on-chip memory, or Block RAMs (BRAMs) ... -
A template system for the efficient compilation of domain abstractions onto reconfigurable computers
(2011)
Text en actes de congrés
Accés restringit per política de l'editorialPast research has addressed the issue of using FPGAs as accelerators for HPC systems. However, writing low level code for an efficient, portable and scalable architecture altogether has been always a ... -
Acceleració d'una aplicació de detecció facial mitjançant FPGA
(Universitat Politècnica de Catalunya, 2017)
Treball Final de Grau
Accés obertActualment, les aplicacions que basen el seu funcionament en el processament d'imatges requereixen d'un gran nivell de còmput. Tot i que al llarg del temps s'han desenvolupat diversos algoritmes per intentar ... -
Accelerating Halide on an FPGA
(Universitat Politècnica de Catalunya, 2023-05-15)
Projecte Final de Màster Oficial
Accés obert
Realitzat a/amb: Kyūshū DaigakuImage processing and, more generally, array processing play an essential role in modern life: from applying filters to the images that we upload to social media to running object detection algorithms on self-driving cars. ... -
Accelerating SpMV on FPGAs through block-row compress: a task-based approach
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Comunicació de congrés
Accés obertSparse Matrix-Vector multiplication (SpMV), computing y=α⋅A×x+β⋅y where y,x are dense vectors, α,β two scalar constants, and A is a sparse matrix, is a key kernel in many HPC applications. It exhibits a kind of memory ... -
Acelerador hardware para procesado vectorial de datos
(Universitat Politècnica de Catalunya, 2016-07)
Projecte/Treball Final de Carrera
Accés restringit per decisió de l'autorEn el procesado masivo de la información se emplean técnicas de paralelización y procesadores vectoriales para trabajar con grandes volúmenes de datos. La información se suele encontrar almacenada en memorias externas ... -
AER communication for spiking neural network emulation on a microprocessor
(Universitat Politècnica de Catalunya, 2023-10-17)
Treball Final de Grau
Accés obertEn aquest treball s'estudia un sistema de comunicació basat en el protocol AER (Address event representation) per a una xarxa neuronal del tipus spiking. Per fer-ho, en aquest projecte es dissenyen, utilitzant VHDL, les ... -
Aggressive undervolting of FPGAs : power & reliability trade-offs
(Universitat Politècnica de Catalunya, 2018-11-19)
Tesi
Accés obertIn this work, we evaluate aggressive undervolting, i.e., voltage underscaling below the nominal level to reduce the energy consumption of Field Programmable Gate Arrays (FPGAs). Usually, voltage guardbands are added by ... -
AIG transformations to improve LUT mapping for FPGAs
(Universitat Politècnica de Catalunya, 2022-06-28)
Projecte Final de Màster Oficial
Accés obertA Field-Programmable Gate Array (FPGA) is a general re-configurable device for implementing logic circuits. This technology is extensively used for prototyping circuits due to its cost and speed. The underlying implementation ... -
AMC: Advanced Multi-accelerator Controller
(2015-01)
Article
Accés obertThe rapid advancement, use of diverse architectural features and introduction of High Level Synthesis (HLS) tools in FPGA technology have enhanced the capacity of data-level parallelism on a chip. A generic FPGA based HLS ... -
Amplificador digital classe D amb reducció de soroll de quantificació
(Universitat Politècnica de Catalunya, 2019-07-03)
Treball Final de Grau
Accés obertEn aquest projecte es desenvolupa un amplificador d’àudio classe D amb especial èmfasi en la reducció del soroll de quantificació. Tot el tractament del senyal és digital des de la font fins a l’última l’etapa i es realitza ... -
An architectural journey into RISC architectures for HPC workloads
(Universitat Politècnica de Catalunya, 2019-01-28)
Projecte Final de Màster Oficial
Accés obert
Realitzat a/amb: Barcelona Supercomputing CenterThe thesis evaluates the current state-of-the-art of RISC architectures in HPC. Studying the performance, power, and energy to solution in heterogeneous SoCs. For the evaluation 2 arm platforms (CPU+GPU, CPU+FPGA), 1 RISC-V ... -
An architecture for real-time arbitrary and variable sampling rate conversion with application to the processing of harmonic signals
(2020-05)
Article
Accés obertThe paper presents a new solution for sampling rate conversion and processing of harmonic signals with known but possibly varying fundamental frequency. This problem is commonly found in particle accelerators, for tracking ... -
An enegy-efficient FPGA accelerator for convolutional neural networks
(Universitat Politècnica de Catalunya, 2018-10-25)
Projecte Final de Màster Oficial
Accés obertThis project focuses on a state-of-the-art DNN specifically build for image clas sification. We develop a new architecture design that will run on an experimental Intel accelerator platform called HARP. We obtain low-power ...
