• Design and implementation of an out of order execution engine of floating point arithmetic operations 

      Ramírez Lazo, Cristóbal (Universitat Politècnica de Catalunya, 2016-02-04)
      Projecte Final de Màster Oficial
      Accés obert
      Realitzat a/amb:   Instituto Politécnico Nacional. Centro de Investigación en Computación
      In this thesis, work is undertaken towards the design in hardware description languages and implementation in FPGA of an out of order execution engine of floating point arithmetic operations. This thesis work, is part of ...
    • From FPGA to ASIC: A RISC-V processor experience 

      Rojas Morales, Carlos (Universitat Politècnica de Catalunya, 2019-10-25)
      Projecte Final de Màster Oficial
      Accés obert
      Realitzat a/amb:   Instituto Politécnico Nacional. Centro de Investigación en Computación
      This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC.