Exploració per autor "Ishikawa, Yutaka"
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Dynamic Adaptable Asynchronous Progress Model for MPI RMA Multiphase Applications
Si, Min; Peña, Antonio J.; Hammond, Jeff; Balaji, Pavan; Takagi, Masamichi; Ishikawa, Yutaka (IEEE, 2018-09-01)
Article
Accés obertCasper is a process-based asynchronous progress model for MPI one-sided communication on multi- and many-core architectures. The one-sided communication is not truly one-sided in most MPI implementations: the target process ... -
On the applicability of PEBS based online memory access tracking for heterogeneous memory management at scale
Roca Nonell, Aleix; Gerofi, Balazs; Bautista-Gomez, Leonardo; Martinet, Dominique; Beltran Querol, Vicenç; Ishikawa, Yutaka (Association for Computing Machinery (ACM), 2018-11)
Comunicació de congrés
Accés obertOperating systems have historically had to manage only a single type of memory device. The imminent availability of heterogeneous memory devices based on emerging memory technologies confronts the classic single memory ...