Now showing items 41-60 of 141

  • Disseny d'una estació per al monitoratge de variables ambientals 

    Tarrats Galocha, Jordi (Universitat Politècnica de Catalunya, 2018-05)
    Bachelor thesis
    Open Access
    En aquest projecte es realitzarà el disseny, la fabricació i la programació d’un enregistrador de dades (datalogger) que s’utilitzarà per a la mesura de variables ambientals. El sistema serà capaç de monitorar les variables ...
  • Disseny d'un microprocessador 

    Montané Sala, Ivan (Universitat Politècnica de Catalunya, 2011-06-15)
    Master thesis (pre-Bologna period)
    Restricted access - author's decision
    En aquest projecte final de carrera dissenyarem i implantarem un microprocessador dins d‟una FPGA utilitzant el llenguatge d‟alt nivell VHDL. Es dissenyarà un microprocessador amb un nucli de vuit bits i amb dotze bits per ...
  • Disseny d'un sistema de test per electrodomèstics a través d'una passarel·la Bluetooth-Egobus (Hardware i aplicació per a mòbil) 

    Castells Soriano, Jordi; Oller Herranz, Jordi (Universitat Politècnica de Catalunya, 2011-07-07)
    Master thesis
    Open Access
    Català: L'objectiu principal d'aquest projecte és dissenyar una eina de test / diagnosis d'electrodomèstics, en el cas que aplica es treballarà amb una rentadora, i que pugui ser utilitzada tant pel S.A.T. (Servei d'Assistència ...
  • Disseny i Construcció d'un DataLogger basat en DSP 

    Fonseca Dalmau, Josep (Universitat Politècnica de Catalunya, 2013-12-05)
    Master thesis (pre-Bologna period)
    Open Access
    The lack or poor distribution of energy is one of the most serious problems that is suffered by a quarter of the world's population today. There still exist a violation of a fundamental right of humanity, accessing energy ...
  • Disseny i Implementació d'una jerarquia de memòria en un processador MIPS 

    Riera Villanueva, Marc (Universitat Politècnica de Catalunya, 2013-06-18)
    Bachelor thesis
    Open Access
    [CATALÀ] Primer s'explicarà breument l'arquitectura d'un MIPS, la jerarquia de memòria i el funcionament de la cache. Posteriorment s'explicarà com s'ha dissenyat i implementat una jerarquia de memòria per a un MIPS ...
  • Disseny i implementació d'un processador SISA-S 

    Ferrer Canal, Jordi (Universitat Politècnica de Catalunya, 2008-07-03)
    Master thesis (pre-Bologna period)
    Open Access
  • Distributing the frontend for temperature reduction 

    Chaparro, Pedro; Magklis, Grigorios; González González, José; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2005)
    Conference report
    Open Access
    Due to increasing power densities, both on-chip average and peak temperatures are fast becoming a serious bottleneck in processor design. This is due to the cost of removing the heat generated, and the performance impact ...
  • Dynamic selective devectorization for efficient power gatting of SIMD units in a HW/SW co-designed enviromment 

    Kumar, Rakesh; Martínez, Alejandro; González Colás, Antonio María (IEEE Computer Society Publications, 2013)
    Conference report
    Open Access
    Leakage power is a growing concern in current and future microprocessors. Functional units of microprocessors are responsible for a major fraction of this power. Therefore, reducing functional unit leakage has received ...
  • Dynamic-vector execution on a general purpose EDGE chip multiprocessor 

    Duric, Milovan; Palomar Pérez, Óscar; Smith, Aaron; Stanic, Milan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo; Burger, Doug; Veidenbaum, Alexander V (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
    Restricted access - publisher's policy
    This paper proposes a cost-effective technique that morphs the available cores of a low power chip multiprocessor (CMP) into an accelerator for data parallel (DLP) workloads. Instead of adding a special-purpose vector ...
  • Early 21st Century processors 

    Vajapeyam, Sriram; Valero Cortés, Mateo (2001-04)
    Article
    Open Access
    The computer architecture arena faces exciting challenges as it attempts to meet the design goals and constraints that new markets, changing applications and fast-moving semiconductor technology impose.
  • Early register release for out-of-order processors with register windows 

    Quiñones, Eduardo; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2007)
    Conference report
    Open Access
    Register windows is an architectural technique that reduces memory operations required to save and restore registers across procedure calls. Its effectiveness depends on the size of the register file. Such register ...
  • Empowering a helper cluster through data-width aware instruction selection policies 

    Unsal, Osman Sabri; Ergin, Oguz; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society, 2006)
    Conference report
    Open Access
    Narrow values that can be represented by less number of bits than the full machine width occur very frequently in programs. On the other hand, clustering mechanisms enable cost- and performance-effective scaling of processor ...
  • Enabling SMT for real-time embedded systems 

    Cazorla Almeida, Francisco Javier; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernandez Prieto, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Conference report
    Open Access
    In order to deal with real time constraints, current embedded processors are usually simple in-order processors with no speculation capabilities to ensure that execution times of applications are predictable. However, ...
  • Energy macro-model for on chip interconnection buses 

    Mendoza Vázquez, Raymundo; Pons Solé, Marc; Moll Echeto, Francisco de Borja; Figueras, Joan (2006-06)
    External research report
    Open Access
    This report presents a fast method of evaluating the power consumption of a bus. Given an on-chip bus driver-interconnection-receiver design of N parallel lines,the objective is to develop its energy consumption macro-model. ...
  • Equip intel·ligent per al marcat porcí 

    Gassol Ramírez, Marc (Universitat Politècnica de Catalunya, 2018-07)
    Bachelor thesis
    Restricted access - confidentiality agreement
  • Error analysis and reduction for a simple sensor-microcontroller interface 

    Custodio Ruiz, Ángel; Pallàs Areny, Ramon; Bragós Bardia, Ramon (IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2001-12-31)
    Article
    Open Access
    Error analysis of a resistive sensor-to-microcontroller interface based on pulse-width modulation and time–ratio measurement shows that internal input and output resistances in microcontroller digital ports produce zero, ...
  • ¿Es verdad que esto se acaba? 

    Barceló Garcia, Miquel (2000-06)
    Article
    Open Access
  • Evaluating the effect of last-level cache sharing on integrated GPU-CPU systems with heterogeneous applications 

    García Flores, Víctor; Gomez Luna, J.; Grass, Thomas Dieter; Rico, Alejandro; Ayguadé Parra, Eduard; Pena, A. J. (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Restricted access - publisher's policy
    Heterogeneous systems are ubiquitous in the field of High- Performance Computing (HPC). Graphics processing units (GPUs) are widely used as accelerators for their enormous computing potential and energy efficiency; ...
  • Evaluating the impact of future memory technologies in the design of multicore processors 

    López Paradís, Guillem (Universitat Politècnica de Catalunya, 2017-01)
    Bachelor thesis
    Open Access
    "It’s the Memory, Stupid!" In 1996, Richard Sites, one of the fathers of Computer Architecture and lead designer of the DEC alpha, wrote a paper [36] with the title above. In that paper he realized that the only important ...
  • Explaining dynamic cache partitioning speed ups 

    Moreto Planas, Miquel; Cazorla, Francisco; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2007-01)
    Article
    Open Access
    Cache partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, ...