Exploració per autor "Ramírez Bellido, Alejandro"
Ara es mostren els items 41-60 de 93
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Latency tolerant branch predictors
(IEEE Press, 2003)
Text en actes de congrés
Accés obertThe access latency of branch predictors is a well known problem of fetch engine design. Prediction overriding techniques are commonly accepted to overcome this problem. However, prediction overriding requires a complex ... -
Long DNA sequence comparison on multicore architectures
(Springer Verlag, 2010)
Text en actes de congrés
Accés restringit per política de l'editorialBiological sequence comparison is one of the most important tasks in Bioinformatics. Due to the growth of biological databases, sequence comparison is becoming an important challenge for high performance computing, especially ... -
Mapping stream programs onto heterogeneous multiprocessor systems
(ACM Press, NY, 2009)
Comunicació de congrés
Accés restringit per política de l'editorialThis paper presents a partitioning and allocation algorithm for an iterative stream compiler, targeting heterogeneous multiprocessors with constrained distributed memory and any communications topology. We introduce a ... -
Marco para el desarrollo de la competencia transversal "comunicación eficaz"
(Universidad de Sevilla. Escuela Técnica Superior de Ingeniería Informática, 2011-07-05)
Comunicació de congrés
Accés obertHay bastante consenso entre los profesores y los empleadores sobre la importancia que tiene para los ingenieros saberse comunicar. También hay consenso respecto a las bajas capacidades comunicativas de nuestros titulados. ... -
Marco para el desarrollo de la competencia transversal "Comunicación Eficaz"
(IEEE. Sociedad de Educación. Capítulos Español, Portugués, Colombiano y Brasileño, 2013)
Capítol de llibre
Accés restringit per política de l'editorialHay bastante consenso entre los profesores y los empleadores sobre la importancia que tiene para los ingenieros saberse comunicar. También hay consenso respecto a las bajas capacidades comunicativas de nuestros titulados. ... -
Maximizing multithreaded multicore architectures through thread migrations
(2009)
Report de recerca
Accés obertHeterogeneity in general-purpose workloads often end up in non optimal per-thread hardware resource usage. The current trend towards multicore architectures, containing several multithreaded cores, increases the need of a ... -
MFLUSH: handling long-latency loads in SMT on-chip multiprocessors
(IEEE Computer Society Publications, 2008)
Text en actes de congrés
Accés obertNowadays, there is a clear trend in industry towards employing the growing amount of transistors on chip in replicating execution cores (CMP), where each core is Simultaneous Multithreading (SMT). State-of-the-art ... -
MLP-aware dynamic cache partitioning
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Comunicació de congrés
Accés obertThe limitation imposed by instruction-level parallelism (ILP) has motivated the use of thread-level parallelism (TLP) as a common strategy for improving processor performance. TLP paradigms such as simultaneous multithreading ... -
Multicore resource management
(2008-06)
Article
Accés obertCurrent resource management mechanisms and policies are inadequate for future multicore systems. Instead, a hardware/software interface based on the virtual private machine abstraction would allow software policies to ... -
On the problem of minimizing workload execution time in SMT processors
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Text en actes de congrés
Accés obertMost research work on (simultaneous multithreading processors) SMTs focuses on improving throughput and/or fairness, or on prioritizing some threads over others in a workload. In this paper, we discuss a new problem not ... -
On the scalability of 1- and 2-dimensional SIMD extensions for multimedia applications
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertSIMD extensions are the most common technique used in current processors for multimedia computing. In order to obtain more performance for emerging applications SIMD extensions need to be scaled. In this paper we perform ... -
On the simulation of large-scale architectures using multiple application abstraction levels
(2012-01-23)
Article
Accés restringit per política de l'editorialSimulation is a key tool for computer architecture research. In particular, cycle-accurate simulators are extremely important for microarchitecture exploration and detailed design decisions, but they are slow and, so, not ... -
On-Chip memories, the OS perspective
(2008-06-04)
Text en actes de congrés
Accés obertThis paper is a work in progress study of the operating system services required to manage on-chip memories. We are evaluating different CMP on-chip memories configurations. Chip-MultiProcessors (CMP) architectures ... -
Online prediction of applications cache utility
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Text en actes de congrés
Accés obertGeneral purpose architectures are designed to offer average high performance regardless of the particular application that is being run. Performance and power inefficiencies appear as a consequence for some programs. ... -
Optimization of instruction fetch for decision support workloads
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Text en actes de congrés
Accés obertInstruction fetch bandwidth is feared to be a major limiting factor to the performance of future wide-issue aggressive superscalars. In this paper, we focus on database applications running decision support workloads. We ... -
Parallel H.264 decoding on an embedded multicore processor
(Springer-Verlag, Berlin, Heidelberg,, 2009-01-28)
Text en actes de congrés
Accés restringit per política de l'editorialIn previous work the 3D-Wave parallelization strategy was proposed to increase the parallel scalability of H.264 video decoding. This strategy is based on the observation that inter-frame dependencies have a limited spatial ... -
Parallel processing in biological sequence comparison using general purpose processors
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertThe comparison and alignment of DNA and protein sequences are important tasks in molecular biology and bioinformatics. One of the most well known algorithms to perform the string-matching operation present in these tasks ... -
Parallel scalability of video decoders
(2009-11)
Article
Accés restringit per política de l'editorialAn important question is whether emerging and future applications exhibit sufficient parallelism, in particular thread-level parallelism, to exploit the large numbers of cores future chip multiprocessors (CMPs) are ... -
Parallelizing general histogram application for CUDA architectures
(IEEE Computational Intelligence Society, 2013)
Text en actes de congrés
Accés restringit per política de l'editorialHistogramming is a tool commonly used in data analysis. Although its serial version is simple to implement, providing an efficient and scalable way to parallelize it can be challenging. This especially holds in case of ... -
Performance analysis of sequence alignment applications
(Institute of Electrical and Electronics Engineers (IEEE), 2006)
Text en actes de congrés
Accés obertAdvances in molecular biology have led to a continued growth in the biological information generated by the scientific community. Additionally, this area has become a multi-disciplinary field, including components of ...
