Now showing items 41-60 of 151

    • EOmesh: combined flow balancing and deterministic routing for reduced WCET estimates in embedded real-time systems 

      Cardona Nadal, Jordi; Abella Ferrer, Jaume; Hernández Luz, Carles; Cazorla Almeida, Francisco Javier (2018-07-17)
      Article
      Open Access
      The increasing performance needs in critical real-time embedded systems (CRTES) can only be satisfied with the use of high-performance manycore processors. While NoC-based manycore systems are popular in the high-performance ...
    • Evaluating the computational capabilities of embedded multicore and GPU platforms for on-board image processing 

      Rodríguez Ferrández, Iván; Kosmidis, Leonidas; Trompouki, Matina Maria; Steenari, David; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2023)
      Conference report
      Open Access
      On-board Image Processing is one of the most computationally intensive tasks performed in space payload processing. With the constant increase in the resolution of optical sensors, new powerful architectures are needed for ...
    • Event monitor validation in high-integrity systems 

      Pujol Torramorell, Roger; Vilardell Moreno, Sergi; Mezzetti, Enrico; Hassan, Mohamed; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2024)
      Conference report
      Open Access
      Platforms for modern embedded systems equip an increasing number of high-performance features to provide the required levels of performance. Timing analysis solutions handle the complexity of these platforms by relying on ...
    • Evolutionary system for prediction and optimization of hardware architecture performance 

      Castillo, Pedro Angel; Merelo, Juan Julián; Moretó Planas, Miquel; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo; Mora, Antonio; Laredo, Juan Luís; McKee, Sally (2008-06)
      Conference report
      Open Access
      The design of computer architectures is a very complex problem. The multiple parameters make the number of possible combinations extremely high. Many researchers have used simulation, although it is a slow solution since ...
    • Experimental analysis on the NXP’s T2080 cache coherence: a step towards MPSoCs in critical systems 

      Pujol, Roger; Hassan, Mohamed; Cazorla Almeida, Francisco Javier (Barcelona Supercomputing Center, 2022-05)
      Conference report
      Open Access
      The adoption of complex MPSoCs in critical real-time embedded systems [1], [2] mandates a detailed analysis of their architecture to facilitate certification [3]. This analysis is hindered by the lack of a thorough ...
    • Fitting processor architectures for measurement-based probabilistic timing analysis 

      Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Vardanega, Tullio; Hernández, Carles; Gianarro, Andrea; Broster, Ian; Cazorla Almeida, Francisco Javier (2016-11-01)
      Article
      Open Access
      The pressing market demand for competitive performance/cost ratios compels Critical Real-Time Embedded Systems industry to employ feature-rich hardware. The ensuing rise in hardware complexity however makes worst-case ...
    • GMAI: Understanding and exploiting the internals of GPU resource allocation in critical systems 

      Calderón Torres, Alejandro Josué; Kosmidis, Leonidas; Nicolás Ramírez, Carlos Fernando; Cazorla Almeida, Francisco Javier; Onaindia, Peio (2020-09)
      Article
      Open Access
      Critical real-time systems require strict resource provisioning in terms of memory and timing. The constant need for higher performance in these systems has led industry to recently include GPUs. However, GPU software ...
    • GPU devices for safety-critical systems: a survey 

      Pérez Cerrolaza, Jon; Abella Ferrer, Jaume; Kosmidis, Leonidas; Calderón Torres, Alejandro Josué; Cazorla Almeida, Francisco Javier; Flores Barroso, José Luis (Association for Computing Machinery (ACM), 2023-07)
      Article
      Open Access
      Graphics Processing Unit (GPU) devices and their associated software programming languages and frameworks can deliver the computing performance required to facilitate the development of next-generation high-performance ...
    • GPU4S: Embedded GPUs in Space 

      Kosmidis, Leonidas; Lachaize, Jérôme; Abella Ferrer, Jaume; Notebaert, Olivier; Cazorla Almeida, Francisco Javier; Steenari, David (Institute of Electrical and Electronics Engineers (IEEE), 2019)
      Conference report
      Open Access
      Following the same trend of automotive and avionics, the space domain is witnessing an increase in the on-board computing performance demands. This raise in performance needs comes from both control and payload parts of ...
    • GPU4S: Embedded GPUs in Space - Latest project updates 

      Kosmidis, Leonidas; Rodríguez Ferrandez, Iván; Jover Álvarez, Álvaro; Alcaide Portet, Sergi; Lachaize, Jérôme; Abella Ferrer, Jaume; Notebaert, Olivier; Cazorla Almeida, Francisco Javier; Steenari, David (2020-09)
      Article
      Open Access
      Following the trend of other safety-critical industries like automotive and avionics, the space domain is witnessing an increase in the on-board computing performance demands. This raise in performance needs comes from ...
    • HRM: merging hardware event monitors for improved timing analysis of complex MPSoCs 

      Vilardell Moreno, Sergi; Serra Mochales, Isabel; Santalla, Roberto; Mezzetti, Enrico; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (2020-11)
      Article
      Open Access
      The Performance Monitoring Unit (PMU) in MPSoCs is at the heart of the latest measurement-based timing analysis techniques in Critical Embedded Systems. In particular, hardware event monitors (HEMs) in the PMU are used as ...
    • HWP: hardware support to reconcile cache energy, complexity, performance and WCET estimates in multicore real-time systems 

      Benedicte Illescas, Pedro; Hernandez, C.; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2018)
      Conference report
      Open Access
      High-performance processors have deployed multilevel cache (MLC) systems for decades. In the embedded real-time market, the use of MLC is also on the rise, with processors for future systems in space, railway, avionics and ...
    • Implicit vs. explicit resource allocation in SMT processors 

      Cazorla Almeida, Francisco Javier; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernandez Garcia, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
      Conference report
      Open Access
      In a simultaneous multithreaded (SMT) architecture, the front end of a superscalar is adapted in order to be able to fetch from several threads while the back end is shared among the threads. In this paper, we describe ...
    • Improving early design stage timing modeling in multicore based real-time systems 

      Trilla, David; Jalle Ibarra, Javier; Fernández, Mikel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference report
      Open Access
      This paper presents a modelling approach for the timing behavior of real-time embedded systems (RTES) in early design phases. The model focuses on multicore processors - accepted as the next computing platform for RTES - ...
    • Improving performance guarantees in wormhole mesh NoC designs 

      Panic, Milos; Hernández, Carles; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference report
      Open Access
      Wormhole-based mesh Networks-on-Chip (wNoC) are deployed in high-performance many-core processors due to their physical scalability and low-cost. Delivering tight and time composable Worst-Case Execution Time (WCET) estimates ...
    • Improving time-randomized cache design 

      Benedicte Illescas, Pedro; Hernández Gañán, Carlos; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Barcelona Supercomputing Center, 2018-04-24)
      Conference report
      Open Access
      Enabling timing analysis for caches has been pursued by the critical real-time embedded systems (CRTES) community for years due to their potential to reduce worstcase execution times (WCET). Measurement-based protabilistic ...
    • Improving Timing-Related Guarantees for Main Memory in Multicore Critical Embedded Systems 

      Fernández de Lecea, Asier; Hassan, Mohamed; Mezzetti, Enrico; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2023)
      Conference lecture
      Open Access
      Main memory is one of the most complex resources to analyze in multicore-based embedded real-time systems, with contention in the memory controller and the timing constraints of the main memory device as the main contributors ...
    • Increasing multicore system efficiency through intelligent bandwidth shifting 

      Jiménez, Víctor; Buyuktosunoglu, Alper; Bose, Pradip; O'Connell, Francis P.; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2015)
      Conference report
      Restricted access - publisher's policy
      Memory bandwidth is a crucial resource in computing systems. Current CMP/SMT processors have a significant number of cores and they can run many threads concurrently. This large thread count adds high pressure to the memory ...
    • Increasing testing robustness of GPU software in embedded critical systems 

      Barrera Herrera, Javier Enrique; Kosmidis, Leonidas; Mezzetti, Enrico; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2024)
      Conference lecture
      Open Access
      Critical autonomous systems build on massively parallel software (e.g., AI software) requiring accelerators like GPUs. However, code coverage requirements imposed by safety standards intended for sequential code are ...
    • IntPred: flexible, fast, and accurate object detection for autonomous driving systems 

      Tabani, Hamid; Fusi, Matteo; Kosmidis, Leonidas; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2020)
      Conference report
      Open Access
      Deep Neural-Network (DNN) based Object Detection is one of the most important and time-consuming stages of Autonomous Driving software in cars. In non-critical domains, the performance and energy requirements of object ...