Now showing items 41-51 of 51

  • Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation 

    Rana, Manish; Canal Corretger, Ramon; Amat Bertran, Esteve; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Open Access
    Bio-medical wearable devices restricted to their small-capacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, ...
  • Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation 

    Rana, Manish; Canal Corretger, Ramon; Amat Bertran, Esteve; Rubio Sola, Jose Antonio (2017-03-01)
    Article
    Open Access
    Bio-medical wearable devices restricted to their small-capacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, ...
  • Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm 

    Amat Bertran, Esteve; García Almudéver, Carmen; Aymerich, N.; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2014-10-01)
    Article
    Open Access
    3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm ...
  • Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level 

    Amat, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Conference lecture
    Restricted access - publisher's policy
    This paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10 nm FinFET devices. The use of ...
  • SyRA: early system reliability analysis for cross-layer soft errors resilience in memory arrays of microprocessor systems 

    Vallero, Alessandro; Savino, Alessandro; Chatzidimitriou, Athanansios; Kaliorakis, Manolis; Kooli, Maha; Riera Villanueva, Marc; Di Natale, Giorgio; Bosio, Alberto; Canal Corretger, Ramon; Gizopoulos, Dimitris; Di Carlo, Stefano; Anglada Sanchez , Martí; González Colás, Antonio María; Mariani, R. (Institute of Electrical and Electronics Engineers (IEEE), 2018-01-01)
    Article
    Open Access
    Cross-layer reliability is becoming the preferred solution when reliability is a concern in the design of a microprocessor-based system. Nevertheless, deciding how to distribute the error management across the different ...
  • The contribution of Type IA supernovae to the galactic iron abundances 

    Bravo Guil, Eduardo; Isern Vilaboy, Jordi; Canal Corretger, Ramon (1993-03)
    Article
    Open Access
    The thermonuclear explosion of a mass-accreting white dwarf in a close binary system is thought to be at the origin of Type Ia supernovae. Standard models, which ignite carbon at densities higher than 2-4 x 10 exp 9 g/cu ...
  • TRAMS Project: variability and reliability of SRAM memories in sub-22nm bulk-CMOS technologies 

    Canal Corretger, Ramon; Rubio Sola, Jose Antonio; ASenov, Asen; Brown, Andrew; Miranda, Miguel; Zuber, Paul; González Colás, Antonio María; Vera Rivera, Francisco Javier (Elsevier, 2011-12-22)
    Article
    Restricted access - publisher's policy
    The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this ...
  • Using coherence information and decay techniques to optimize L2 cache leakage in CMPs 

    Monchiero, Matteo; Canal Corretger, Ramon; González Colás, Antonio María (IEEE Computer Society, 2009)
    Conference report
    Open Access
    This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this case, coherence must be enforced in all ...
  • Variability impact on on-chip memory data paths 

    Amat Bertran, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2014)
    Conference lecture
    Open Access
    Process variations have a large impact on device and circuit reliability and performance. Few studies are focused on their impact on more complex systems, as for example their influence in a data path. In our study, the ...
  • Very low power pipelines using significance compression 

    Canal Corretger, Ramon; González Colás, Antonio María; Smith, James E. (Institute of Electrical and Electronics Engineers (IEEE), 2000)
    Conference report
    Open Access
    Data, addresses, and instructions are compressed by maintaining only significant bytes with two or three extension bits appended to indicate the significant byte positions. This significance compression method is integrated ...
  • vPROBE: Variation aware post-silicon power/performance binning using embedded 3T1D cells 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (2010-09-05)
    External research report
    Open Access
    In this paper, we present an on-die post-silicon binning methodology that takes into account the effect of static and dynamic variations and categorizes every processor based on power/performance.The proposed scheme is ...