Exploració per autor "Abella Ferrer, Jaume"
Ara es mostren els items 40-59 de 212
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Contention-aware performance monitoring counter support for real-time MPSoCs
Jalle Ibarra, Javier; Fernández, Mikel; Abella Ferrer, Jaume; Andersson, Jan; Patte, Mathieu; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
Comunicació de congrés
Accés obertTasks running in MPSoCs experience contention delays when accessing MPSoC’s shared resources, complicating task timing analysis and deriving execution time bounds. Understanding the Actual Contention Delay (ACD) each task ... -
Control-flow recovery validation using microarchitectural invariants
Carretero Casado, Javier Sebastián; Abella Ferrer, Jaume; Vera Gómez, Javier; Chaparro Valero, Pedro Alonso (2011)
Text en actes de congrés
Accés restringit per política de l'editorialProcessors' design complexity increases with transistors' growing density. At the same time, market competence requires a decreasing time-to-market, and therefore, reduced validation time. Such time reduction imposes new ... -
Data bus slicing for contention-free multicore real-time memory systems
Jalle Ibarra, Javier; Quiñones, Eduardo; Abella Ferrer, Jaume; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertMemory access contention is one of the main contributors to tasks' execution time variability in real-Time multicores. Existing techniques to control memory contention based on time-sharing memory access do not scale well ... -
De-RISC – Dependable Real-Time Infrastructure for Safety-Critical Computer Systems
Gómez, Francisco; Masmano, Miguel; Nicolau, Vicente; Andersson, Jan; Le Rhun, Jimmy; Trilla, David; Gallego, Felipe; Cabo, Guillem; Abella Ferrer, Jaume (Ada-Europe, 2020-06)
Article
Accés obertThe space domain demands increased performance, reliable and easy to verify and validate platforms tomatch the requirements of highly autonomous missions and systems that need to undergo qualification and certification ... -
De-RISC: A complete RISC-V based space-grade platform
Wessman, Nils-Johan; Malatesta, Fabio; Ribes, Stefano; Andersson, Jan; García Vilanova, Antonio; Masmano Tello, Miguel; Nicolau Gallego, Vicente; Gómez Molinero, Paco; Le Rhun, Jimmy; Alcaide Portet, Sergi; Cabo Pitarch, Guillem; Bas Jalón, Francisco; Benedicte Illescas, Pedro; Mazzocchetti, Fabio; Abella Ferrer, Jaume (Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertThe H2020 EIC-FTI De-RISC project develops a RISC-V space-grade platform to jointly respond to several emerging, as well as longstanding needs in the space domain such as: (1) higher performance than that of monocore and ... -
De-RISC: the First RISC-V space-grade platform for safety-critical systems
Wessman, Nils-Johan; Malatesta, Fabio; Andersson, Jan; Gómez Molinero, Paco; Masmano Tello, Miguel; Nicolau Gallego, Vicente; Le Rhun, Jimmy; Cabo Pitarch, Guillem; Bas Jalón, Francisco; Lorenzo Ortega, Rubén; Sala Sucarrats, Oriol; Trilla Rodríguez, David; Abella Ferrer, Jaume (Institute of Electrical and Electronics Engineers (IEEE), 2021)
Text en actes de congrés
Accés obertThe increasing needs for performance in the space domain for highly autonomous systems calls for more powerful space MPSoCs and appropriate hypervisors to master them. These platforms must adhere to strict reliability, ... -
Deconstructing bus access control policies for real-time multicores
Jalle Ibarra, Javier; Abella Ferrer, Jaume; Quiñones, Eduardo; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialMulticores may satisfy the growing performance requirements of critical Real-Time systems which has made industry to consider them for future real-time systems. In a multicore, the bus contention-control policy plays a key ... -
Design and implementation of a fair credit-based bandwidth sharing scheme for buses
Slijepcevic, Mladen; Hernandez, Carles; Abella Ferrer, Jaume; Cazorla, Francisco J. (Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
Comunicació de congrés
Accés obertFair arbitration in the access to hardware shared resources is fundamental to obtain low worst-case execution time (WCET) estimates in the context of critical real-time systems, for which performance guarantees are essential. ... -
Design and integration of hierarchical-placement multi-level caches for real-Time systems
Benedicte Illescas, Pedro; Hernandez, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés restringit per política de l'editorialEnabling timing analysis in the presence of caches has been pursued by the real-Time embedded systems (RTES) community for years due to cache's huge potential to reduce software's worst-case execution time (WCET). However, ... -
Design of complex circuits using the via-configurable transistor array regular layout fabric
Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (IEEE Computer Society Publications, 2011)
Text en actes de congrés
Accés restringit per política de l'editorialLayout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new ... -
DIMP: A low-cost diversity metric based on circuit path analysis
Alcaide Portet, Sergi; Hernandez, Carles; Roca, Antoni; Abella Ferrer, Jaume (2017)
Text en actes de congrés
Accés obertDiversity has been regarded as a desirable property of redundant instances, since it allows circuits to behave differently in front of a given fault. However, while qualitatively diversity is a well-understood concept, ... -
DReAM: An approach to estimate per-Task DRAM energy in multicore systems
Liu, Qixiao; Moretó Planas, Miquel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (2016-12)
Article
Accés obertAccurate per-task energy estimation in multicore systems would allow performing per-task energy-aware task scheduling and energy-aware billing in data centers, among other applications. Per-task energy estimation is ... -
DReAM: Per-task DRAM energy metering in multicore systems
Liu, Qixiao; Moretó Planas, Miquel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (Springer, 2014)
Text en actes de congrés
Accés obertInteraction across applications in DRAM memory impacts its energy consumption. This paper makes the case for accurate per-task DRAM energy metering in multicores, which opens new paths to energy/performance optimizations, ... -
DTM: degraded test mode for fault-aware probabilistic timing analysis
Slijepcevic, Mladen; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialExisting timing analysis techniques to derive Worst-Case Execution Time (WCET) estimates assume that hardware in the target platform (e.g., the CPU) is fault-free. Given the performance requirements increase in current ... -
Dynamic and execution views to improve validation, testing, and optimization of autonomous driving software
Alcón Doganoc, Miguel; Tabani, Hamid; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Springer Nature, 2023-06)
Article
Accés obertThe adoption of autonomous driving (AD) software executed on high-performance multi-processor systems on chip (MPSoCs) contributes to increasing the overall system’s safety and efficiency. However, existing AD software ... -
Dynamic software randomisation: Lessons learnec from an aerospace case study
Cros, Fabrice; Kosmidis, Leonidas; Wartel, Franck; Morales, David; Abella Ferrer, Jaume; Broster, Ian; Cazorla, Francisco J. (2017-05-15)
Comunicació de congrés
Accés obertTiming Validation and Verification (V&V) is an important step in real-time system design, in which a system's timing behaviour is assessed via Worst Case Execution Time (WCET) estimation and scheduling analysis. For WCET ... -
Efficient cache architectures for reliable hybrid voltage operation using EDC codes
Maric, Bojan; Abella Ferrer, Jaume; Valero Cortés, Mateo (2013)
Text en actes de congrés
Accés obertSemiconductor technology evolution enables the design of sensor-based battery-powered ultra-low-cost chips (e.g., below 1 p) required for new market segments such as body, urban life and environment monitoring. Caches have ... -
Empirical evidence for MPSoCs in critical systems: The case of NXP’s T2080 cache coherence
Pujol Torramorell, Roger; Tabani, Hamid; Abella Ferrer, Jaume; Hassan, Mohamed; Cazorla Almeida, Francisco Javier (IEEE, 2021)
Comunicació de congrés
Accés obertThe adoption of complex MPSoCs in critical real-time embedded systems mandates a detailed analysis their architecture to facilitate certification. This analysis is hindered by the lack of a thorough understanding of the ... -
En-route: on enabling resource usage testing for autonomous driving frameworks
Alcon, Miguel; Tabani, Hamid; Abella Ferrer, Jaume; Kosmidis, Leonidas; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2020-03)
Text en actes de congrés
Accés obertSoftware resource usage testing, including execution time bounds and memory, is a mandatory validation step during the integration of safety-related real-time systems. However, the inherent complexity of Autonomous Driving ... -
Enabling unit testing of already-integrated AI software systems: The case of Apollo for autonomous driving
Alcón Doganoc, Miguel; Tabani, Hamid; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2021)
Text en actes de congrés
Accés obertThe advanced AI-based software used for autonomous driving comprises multiple highly-coupled modules that are data and control dependent. Deploying those already-integrated software frameworks makes unit testing, a fundamental ...