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    • Verification of a floating point reduction unit 

      Díaz Ortega, Iván (Universitat Politècnica de Catalunya, 2021-07-01)
      Bachelor thesis
      Open Access
      This thesis goes around the effort made to verify a submodule of a vector processing unit or VPU. This submodule is the one in charge of performing vector reductions, and due to the nature of some of the reductions, an ...