Now showing items 21-40 of 139

  • Benchmarks en diferents microprocessadors 

    Caubet Gomà, Josep (Universitat Politècnica de Catalunya, 2006-07-19)
    Master thesis (pre-Bologna period)
    Open Access
    The objective of this thesis is to obtain results of benchmarking between different boards; RCM3720 of Rabbit Semiconductor and SNAP and IM3000 of Imsys Technologies. Three different computer languages have been used: C, ...
  • Block disabling characterization and improvements in CMPs operating at ultra-low voltages 

    Ferrerón, Alexandra; Suárez Gracia, Darío; Alastruey, Jesús; Monreal Arnal, Teresa; Viñals Yufera, Víctor (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
    Open Access
    Power density has become the limiting factor in technology scaling as power budget restricts the amount of hardware that can be active at the same time. Reducing supply voltage to ultra-low voltage ranges close to the ...
  • Characterization and modeling of multicast communication in cache-coherent manycore processors 

    Abadal Cavallé, Sergi; Martinez, Raul; Solé Pareta, Josep; Alarcón Cot, Eduardo José; Cabellos Aparicio, Alberto (2016-01-21)
    Article
    Open Access
    The scalability of Network-on-Chip (NoC) designs has become a rising concern as we enter the manycore era. Multicast support represents a particular yet relevant case within this context, mainly due to the poor performance ...
  • Chrysso: an integrated power manager for constrained many-core processors 

    Jha, Sudhanshu Shekhar; Heirman, Wim; Falcón Samper, Ayose Jesus; Carlson, Trevor E.; Van Craeynest, Kenzo; Tubella Murgadas, Jordi; González Colás, Antonio María; Eeckhout, Lieven (Association for Computing Machinery (ACM), 2015)
    Conference report
    Open Access
    Modern microprocessors are increasingly power-constrained as a result of slowed supply voltage scaling (end of Dennard scaling) in conjunction with the transistor density scaling (Moore's Law). Existing many-core power ...
  • Cost-conscious strategies to increase performance of numerical programs on agressive VLIW architectures 

    López Álvarez, David; Llosa Espuny, José Francisco; Valero Cortés, Mateo; Ayguadé Parra, Eduard (2001-10)
    Article
    Open Access
    Loops are the main time-consuming part of numerical applications. The performance of the loops is limited either by the resources offered by the architecture or by recurrences in the computation. To execute more operations ...
  • CPU accounting in CMP processors 

    Luque, Carlos; Moreto Planas, Miquel; Cazorla, Francisco; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortés, Mateo (2009-01)
    Article
    Open Access
    Chip-MultiProcessors (CMP) introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is ...
  • Cursp práctico de microprocesadores con metodología semipresencial 

    Ortega Redondo, Juan Antonio; Romeral Martínez, José Luis; Thomaschewski, J; García Espinosa, Antonio; Cusidó Roura, Jordi; Mon González, Juan (Universitat Politècnica de Catalunya, 2004)
    Conference report
    Open Access
    El objetivo final de esta experiencia es mejorar la docencia impartida por el Departamento de Ingeniería Electrónica en el Campus de Terrassa de la UPC en el área de microprocesadores. La mejora tiene dos ejes fundamentales, ...
  • Decision Support Database Management System Acceleration Using Vector Processor 

    Hayes, Timothy (Universitat Politècnica de Catalunya, 2011-09-20)
    Master thesis
    Open Access
    English: This work takes a top-down approach to accelerating decision support systems (DSS) on x86-64 microprocessors using true vector ISA extensions. First, a state of art DSS database management system (DBMS) is pro ...
  • Delaying physical register allocation trought virtual-physical registers 

    Monreal Arnal, Teresa; González Colás, Antonio María; Valero Cortés, Mateo; González González, José; Viñals Yufera, Víctor (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Conference report
    Open Access
    Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This ...
  • Desarrollo de una plataforma de trabajo para la investigación 

    Blázquez Francisco, Víctor (Universitat Politècnica de Catalunya, 2010-06-22)
    Master thesis (pre-Bologna period)
    Open Access
  • Desarrollo de un sistema basado en MPC8572 Y Linux 

    Gómez Morales, Isaac (Universitat Politècnica de Catalunya, 2009-03-17)
    Master thesis
    Open Access
    Los objetivos a cuya consecución viene a dar respuesta el desarrollo del Proyecto son:Examinación del hardware dado, para ver las características de éste que se puedan explotar. Elegir un sistema operativo, lo menos ...
  • Design and implementation of an ARMv4 tightly coupled multicore in VHDL and validation on a FPGA 

    Ariño Alegre, Carlos (Universitat Politècnica de Catalunya / Technische Universität Berlin, 2012-07-09)
    Master thesis (pre-Bologna period)
    Open Access
    [ANGLÈS] On one hand, few years ago increasing the clock speed was the preferred tactic by manufacturers to gradually increase the performance of computers. However, from certain speeds there are some limitations. Some ...
  • Design of an ammeter for the test of printed circuits 

    Megías Teruel, Francesc (Universitat Politècnica de Catalunya, 2019-01)
    Bachelor thesis
    Open Access
    Design this ammeter from a current sensor. Developing around it a system capable of communicating easily with the user.
  • DIA: A complexity-effective decoding architecture 

    Santana Jaria, Oliverio J.; Falcón Samper, Ayose Jesus; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2009-04)
    Article
    Open Access
    Fast instruction decoding is a true challenge for the design of CISC microprocessors implementing variable-length instructions. A well-known solution to overcome this problem is caching decoded instructions in a hardware ...
  • Direct instruction wakeup for out-of-order processors 

    Ramírez, Marco Antonio; Cristal Kestelman, Adrián; Veidenbaum, Alex; Villa, Luis A; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Conference report
    Open Access
    Instruction queues consume a significant amount of power in high-performance processors, primarily due to instruction wakeup logic access to the queue structures. The wakeup logic delay is also a critical timing parameter. ...
  • Diseño de un dispositivo basado en microprocesador para la identificación de sistemas dinámicos lineales 

    Izquierdo Perálvarez, Alberto (Universitat Politècnica de Catalunya, 2013-09)
    Master thesis (pre-Bologna period)
    Open Access
  • Diseño e implementación de un simulador de una SPU 

    Cabrera Benítez, Daniel (Universitat Politècnica de Catalunya, 2007-07-06)
    Master thesis (pre-Bologna period)
    Open Access
  • Diseño e implementación de un sistema para la detección de vehículos en plazas de parking exterior 

    Hernández Artacho, Israel (Universitat Politècnica de Catalunya, 2016-10)
    Master thesis (pre-Bologna period)
    Restricted access - confidentiality agreement
  • Disseny del software de la centraleta principal del CAT08e, Formula Student elèctric de l'ETSEIB Motorsport 

    Massot Vidal, Xavier (Universitat Politècnica de Catalunya, 2015-06)
    Bachelor thesis
    Open Access
    Aquest projecte tracta sobre el disseny del software de la centraleta principal del CAT08e, vehicle dissenyat i construït per l’ETSEIB Motorsport, un equip d’estudiants d’aquesta escola, amb l’objectiu de competir en el ...
  • Disseny d'una estació per al monitoratge de variables ambientals 

    Tarrats Galocha, Jordi (Universitat Politècnica de Catalunya, 2018-05)
    Bachelor thesis
    Open Access
    En aquest projecte es realitzarà el disseny, la fabricació i la programació d’un enregistrador de dades (datalogger) que s’utilitzarà per a la mesura de variables ambientals. El sistema serà capaç de monitorar les variables ...