Ara es mostren els items 21-40 de 195

    • Beehive: an FPGA-based multiprocessor architecture 

      Arcas Abella, Oriol (Universitat Politècnica de Catalunya, 2009-09-23)
      Projecte Final de Màster Oficial
      Accés obert
      In recent years, to accomplish with the Moore's law hardware and software designers are tending progressively to focus their efforts on exploiting instruction-level parallelism. Software simulation has been essential for ...
    • Benchmarks en diferents microprocessadors 

      Caubet Gomà, Josep (Universitat Politècnica de Catalunya, 2006-07-19)
      Projecte/Treball Final de Carrera
      Accés obert
      The objective of this thesis is to obtain results of benchmarking between different boards; RCM3720 of Rabbit Semiconductor and SNAP and IM3000 of Imsys Technologies. Three different computer languages have been used: C, ...
    • Block disabling characterization and improvements in CMPs operating at ultra-low voltages 

      Ferrerón, Alexandra; Suárez Gracia, Darío; Alastruey, Jesús; Monreal Arnal, Teresa; Viñals Yufera, Víctor (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Text en actes de congrés
      Accés obert
      Power density has become the limiting factor in technology scaling as power budget restricts the amount of hardware that can be active at the same time. Reducing supply voltage to ultra-low voltage ranges close to the ...
    • Characterization and modeling of multicast communication in cache-coherent manycore processors 

      Abadal Cavallé, Sergi; Martinez, Raul; Solé Pareta, Josep; Alarcón Cot, Eduardo José; Cabellos Aparicio, Alberto (2016-01-21)
      Article
      Accés obert
      The scalability of Network-on-Chip (NoC) designs has become a rising concern as we enter the manycore era. Multicast support represents a particular yet relevant case within this context, mainly due to the poor performance ...
    • Chrysso: an integrated power manager for constrained many-core processors 

      Jha, Sudhanshu Shekhar; Heirman, Wim; Falcón Samper, Ayose Jesus; Carlson, Trevor E.; Van Craeynest, Kenzo; Tubella Murgadas, Jordi; González Colás, Antonio María; Eeckhout, Lieven (Association for Computing Machinery (ACM), 2015)
      Text en actes de congrés
      Accés obert
      Modern microprocessors are increasingly power-constrained as a result of slowed supply voltage scaling (end of Dennard scaling) in conjunction with the transistor density scaling (Moore's Law). Existing many-core power ...
    • Control mediante microprocesador de una mano robótica 

      Suárez Carrillo, Miguel Ángel (Universitat Politècnica de Catalunya, 2017-06-22)
      Treball Final de Grau
      Accés restringit per decisió de l'autor
    • Cost-conscious strategies to increase performance of numerical programs on agressive VLIW architectures 

      López Álvarez, David; Llosa Espuny, José Francisco; Valero Cortés, Mateo; Ayguadé Parra, Eduard (2001-10)
      Article
      Accés obert
      Loops are the main time-consuming part of numerical applications. The performance of the loops is limited either by the resources offered by the architecture or by recurrences in the computation. To execute more operations ...
    • CPU accounting in CMP processors 

      Luque, Carlos; Moretó Planas, Miquel; Cazorla, Francisco; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortés, Mateo (2009-01)
      Article
      Accés obert
      Chip-MultiProcessors (CMP) introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is ...
    • Curso práctico de microprocesadores con metodología semipresencial 

      Ortega Redondo, Juan Antonio; Romeral Martínez, José Luis; Thomaschewski, J; García Espinosa, Antonio; Cusidó Roura, Jordi; Mon González, Juan (Universitat Politècnica de Catalunya, 2004)
      Text en actes de congrés
      Accés obert
      El objetivo final de esta experiencia es mejorar la docencia impartida por el Departamento de Ingeniería Electrónica en el Campus de Terrassa de la UPC en el área de microprocesadores. La mejora tiene dos ejes fundamentales, ...
    • Decision Support Database Management System Acceleration Using Vector Processor 

      Hayes, Timothy (Universitat Politècnica de Catalunya, 2011-09-20)
      Projecte Final de Màster Oficial
      Accés obert
      English: This work takes a top-down approach to accelerating decision support systems (DSS) on x86-64 microprocessors using true vector ISA extensions. First, a state of art DSS database management system (DBMS) is pro ...
    • Delaying physical register allocation trought virtual-physical registers 

      Monreal Arnal, Teresa; González Colás, Antonio María; Valero Cortés, Mateo; González González, José; Viñals Yufera, Víctor (Institute of Electrical and Electronics Engineers (IEEE), 1999)
      Text en actes de congrés
      Accés obert
      Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This ...
    • Desarrollo de un sistema basado en MPC8572 Y Linux 

      Gómez Morales, Isaac (Universitat Politècnica de Catalunya, 2009-03-17)
      Projecte Final de Màster Oficial
      Accés obert
      Los objetivos a cuya consecución viene a dar respuesta el desarrollo del Proyecto son:Examinación del hardware dado, para ver las características de éste que se puedan explotar. Elegir un sistema operativo, lo menos ...
    • Desarrollo de una plataforma de trabajo para la investigación 

      Blázquez Francisco, Víctor (Universitat Politècnica de Catalunya, 2010-06-22)
      Projecte/Treball Final de Carrera
      Accés obert
    • Design and implementation of a bootrom in a Linux capable RISC-V processor 

      Garcia Aguilar, Jordi (Universitat Politècnica de Catalunya, 2022-01-26)
      Treball Final de Grau
      Accés obert
      El moviment de codi obert promet revolucionar el món del maquinari igual que el programari ha revolucionat. Gràcies a l'arquitectura de conjunt d'instruccions o ISA (de l'anglès Instruction Set Architecture) RISC-V de codi ...
    • Design and Implementation of a Controller for a Wireless Power Transfer Demonstrator 

      Perich Ibáñez, Daniel (Universitat Politècnica de Catalunya, 2019-06)
      Treball Final de Grau
      Accés obert
      This thesis describes the design and implementation of a controller for a wireless power transfer (WPT) demonstrator. First, the system was simulated to examine the feasibility. Then, an analog control was designed and ...
    • Design and implementation of an ARMv4 tightly coupled multicore in VHDL and validation on a FPGA 

      Ariño Alegre, Carlos (Universitat Politècnica de Catalunya / Technische Universität Berlin, 2012-07-09)
      Projecte/Treball Final de Carrera
      Accés obert
      [ANGLÈS] On one hand, few years ago increasing the clock speed was the preferred tactic by manufacturers to gradually increase the performance of computers. However, from certain speeds there are some limitations. Some ...
    • Design and test of a neural microprocessor 

      Calduch Isaksen, Jan (Universitat Politècnica de Catalunya, 2022-06-28)
      Treball Final de Grau
      Accés obert
      En aquest projecte, es dissenya un microprocessador neuronal per ser implementat en FPGAs. Aquesta tecnologia consisteix en un processador softcore basat en RISC-V descrit amb SystemVerilog que s'utilitza per controlar un ...
    • Design for Testability methodologies applied to a RISC-Vprocessor 

      Fontova Musté, Pau (Universitat Politècnica de Catalunya, 2021-01-29)
      Projecte Final de Màster Oficial
      Accés obert
      The decrease in the size of transistors and technology nodes has made manufacturing processes increasingly difficult and unreliable, Design for Test techniques provide measures to thoroughly test the manufactured device ...
    • Design of a monitoring device for closed protocol fire protection systems 

      Senciales Sánchez, Daniel (Universitat Politècnica de Catalunya, 2020-11-25)
      Treball Final de Grau
      Accés restringit per acord de confidencialitat
    • Design of a multi-phase hysteretic regulator for low voltage applications 

      Cruz Vaquer, Juan (Centre de Publicacions del Campus Nord SCCL (CPET), 2009)
      Text en actes de congrés
      Accés obert