Exploració per tema "Matrius de portes programables per l'usuari"

Ara es mostren els items 21-40 de 82

    • AXIOM: a hardware-software platform for cyber physical systems 

      Mazumdar, Somnath; Ayguadé Parra, Eduard; Bettin, Nicola; Bueno Hedo, Javier; Ermini, Sara; Filgueras Izquierdo, Antonio; Jiménez González, Daniel; Álvarez Martínez, Carlos; Martorell Bofill, Xavier; Montefoschi, Francesco; Oro Garcia, David; Pnevmatikatos, Dionisis; Rizzo, Antonio; Theodoropoulos, Dimitris; Giorgi, Roberto (2016)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Cyber-Physical Systems (CPSs) are widely necessary for many applications that require interactions with the humans and the physical environment. A CPS integrates a set of hardware-software components to distribute, execute ...

    • Calibration of a TDL-TDC with ML methods 

      Costa Cañones, Daniel (Universitat Politècnica de Catalunya, 2022-06-09)
      Projecte Final de Màster Oficial
      Accés restringit per acord de confidencialitat
      Realitzat a/amb:   Politecnico di Milano

    • Can we trust undervolting in FPGA-based deep learning designs at harsh conditions? 

      Koc, Fahrettin; Salami, Behzad; Ergin, Oguz; Unsal, Osman Sabri; Cristal Kestelman, Adrián (2022-05)
      Article
      Accés obert
      As more Neural Networks on Field Programmable Gate Arrays (FPGAs) are used in a wider context, the importance of power efficiency increases. However, the focus on power should never compromise application accuracy. One ...

    • Characterization and optimization of a multi-channel, FPGA-based Time-to-Digital Converter 

      Compte Prades, Joel (Universitat Politècnica de Catalunya, 2023-09-06)
      Projecte Final de Màster Oficial
      Accés obert
      Realitzat a/amb:   Institut de Ciències Fotòniques (ICFO)
      High-resolution time measurement is a fundamental building block on a wide variety of applications such as time-of-flight based systems, single-photon microscopy and quantum communications. FPGA-based TDCs are the preferred ...

    • Considerations in using OpenCL on GPUs and FPGAs for throughput-oriented genomics workloads 

      Cadenelli, Nicola; Jaksic, Zoran; Polo Bardés, Jordà; Carrera Pérez, David (Elsevier, 2019-05)
      Article
      Accés obert
      The recent upsurge in the available amount of health data and the advances in next-generation sequencing are setting the ground for the long-awaited precision medicine. To process this deluge of data, bioinformatics workloads ...

    • Demonstrating reduced-voltage FPGA-based neural network acceleration for power-efficiency 

      Onural, Erhan Baturay; Yuksel, Ismail Emir; Salami, Behzad (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Comunicació de congrés
      Accés obert
      This demo aims to demonstrate undervolting below the nominal level set by the vendor for off-the-shelf FPGAs running Deep Neural Networks (DNNs), to achieve power-efficiency. FPGAs are becoming popular [1-4], thanks to ...

    • Design and Development of an FPGA-based Medical EIS System 

      Montsech Bravo, Isaac (Universitat Politècnica de Catalunya, 2022-10-27)
      Projecte Final de Màster Oficial
      Accés obert
      Electrical impedance spectroscopy is a powerful technique which can be used to characterize properties of many materials, including biological tissues. In medical applications, it is typically used as a complementary tool ...

    • Design, implementation and evaluation of post-quantum cryptography accelerators in 22nm FDSOI technology 

      Carril I Gil, Xavier (Universitat Politècnica de Catalunya, 2023-02-02)
      Projecte Final de Màster Oficial
      Accés obert
      This thesis aims to design and implement a Post-Quantum Cryptographic (PQC) algorithm accelerator to integrate it inside a System On Chip (SoC) for FPGA and ASIC targets. The accelerated PQC algorithm is called CRYSTALS-Kyber, ...

    • Development and implementation of real-time control strategies based on FPGA 

      Prats Moreu, Santi (Universitat Politècnica de Catalunya, 2020-07-22)
      Treball Final de Grau
      Accés obert

    • Development of a benchmark suite for large vector architectures into a continuous integration workflow 

      Bros Esqueu, Rafel Albert (Universitat Politècnica de Catalunya, 2022-06-28)
      Treball Final de Grau
      Accés obert
      Realitzat a/amb:   Barcelona Supercomputing Center
      En el món del "High-Performance Computing", el processador és essencial. Recentment, Europa està fent grans esforços en promoure tecnologia europea. La "European Processor Initiative" sorgeix d'aquest esforç. Com a part ...

    • Diseño de un linealizador adaptativo y analógico para amplificadores de potencia 

      Bertran Albertí, Eduardo; Zozaya, A; Montoro López, Gabriel; Berenguer Sau, Jordi (Congrega, 2003)
      Text en actes de congrés
      Accés obert

    • Disseny d'un microprocessador en una FPGA basat en màquines algorítmiques 

      Gil Viudez, Alexandre (Universitat Politècnica de Catalunya, 2023-07-12)
      Treball Final de Grau
      Accés obert
      En el present projecte es proposa desenvolupar un processador a través de la metodologia de màquines algorítmiques. Posteriorment, s’implementa en una FPGA per validar el funcionament del disseny. L’arquitectura del set ...

    • Disseny d'una eina de diagnòstic CAN basada en FPGA 

      Galindo Hurtado, Carlos (Universitat Politècnica de Catalunya, 2017-07-10)
      Projecte Final de Màster Oficial
      Accés obert
      L’objectiu d’aquest projecte és dissenyar i implementar un sistema de comunicació CAN (Controller Area Network) de baix cost sobre una plataforma FPGA complint al màxim amb la normativa ISO 11898. La metodologia empleada ...

    • Disseny i test d’un core RISC per a microcontrolador 

      Aguiló Domínguez, David (Universitat Politècnica de Catalunya, 2020-07-15)
      Treball Final de Grau
      Accés obert
      En aquest treball s’ha realitzat el disseny i les proves de funcionament per simulació d’un microcontrolador, capaç d’executar totes les instruccions del set d’instruccions AVR1 del fabricant de microcontroladors Atmel. ...

    • Evaluating built-in ECC of FPGA on-chip memories for the mitigation of undervolting faults 

      Salami, Behzad; Unsal, Osman Sabri; Cristal Kestelman, Adrián (Institute of Electrical and Electronics Engineers (IEEE), 2019)
      Text en actes de congrés
      Accés obert
      Voltage underscaling below the nominal level is an effective solution for improving energy efficiency in digital circuits, e.g., Field Programmable Gate Arrays (FPGAs). However, further undervolting below a safe voltage ...

    • Exact and heuristic allocation of multi-kernel applications to multi-FPGA platforms 

      Shan, Junnan; Casu, Mario R.; Cortadella, Jordi; Lavagno, Luciano; Lazarescu, Mihai T. (Association for Computing Machinery (ACM), 2019-06)
      Text en actes de congrés
      Accés obert
      FPGA-based accelerators demonstrated high energy efficiency compared to GPUs and CPUs. However, single FPGA designs may not achieve sufficient task parallelism. In this work, we optimize the mapping of high-performance ...

    • Exceeding conservative limits: A consolidated analysis on modern hardware margins 

      Papadimitriou, George; Chatzidimitriou, Athanansios; Gizopoulos, Dimitris; Reddi, Vijay Janapa; Leng, Jingwen; Salami, Behzad; Unsal, Osman Sabri; Cristal Kestelman, Adrián (2020-06)
      Article
      Accés obert
      Modern large-scale computing systems (data centers, supercomputers, cloud and edge setups and high-end cyber-physical systems) employ heterogeneous architectures that consist of multicore CPUs, general-purpose many-core ...

    • Extension and improvement of a PCIe-based FPGA environment for testing HPC architectures 

      Querol De Porras, Andrea (Universitat Politècnica de Catalunya, 2023-06-29)
      Projecte Final de Màster Oficial
      Accés obert
      The European Processor Initiative (EPI) is a European project that performs research to advance High-Performance Computing (HPC) through the development of European technology. EPI aims at the development of a general-purpose ...

    • Fast energy-optimal multi-kernel DNN-like application allocation on multi-FPGA platforms 

      Shan, Junnan; Lazarescu, Mihai T.; Cortadella, Jordi; Lavagno, Luciano; Casu, Mario R. (2022-04)
      Article
      Accés obert
      Platforms with multiple Field Programmable Gate Arrays (FPGAs), such as Amazon Web Services (AWS) F1 instances, can efficiently accelerate multi-kernel pipelined applications, e.g., Convolutional Neural Networks for machine ...

    • Field programmable gate array-based smart switch to avoid inrush current in PV installations 

      Martínez Figueroa, Gerardo de Jesús; Córcoles López, Felipe; Bogarra Rodríguez, Santiago (Multidisciplinary Digital Publishing Institute (MDPI), 2024-02-01)
      Article
      Accés obert
      This paper introduces an FPGA-based implementation of a smart switch designed to avoid inrush currents occurring during the connection of single-phase transformers utilized in grid-connected photovoltaic (PV) systems. The ...