Exploració per tema "Logic circuits"
Ara es mostren els items 21-40 de 43
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Evaluation of A+B=K conditions without carry propagation
(Institute of Electrical and Electronics Engineers (IEEE), 1992-11)
Article
Accés obertThe response time of parallel adders is mainly determined by the carry propagation delay. The evaluation of conditions of the type A+B=K is addressed. Although an addition is involved in the comparison, it is shown that ... -
From synchronous to asynchronous: an automatic approach
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Text en actes de congrés
Accés obertThis paper presents a methodology to derive asynchronous circuits from optimized synchronous circuits by replacing the clock distribution tree by a handshaking network. A case study shows the applicability of the method ... -
Hierarchical gate-level verification of speed-independent circuits
(Institute of Electrical and Electronics Engineers (IEEE), 1995)
Text en actes de congrés
Accés obertThis paper presents a method for the verification of speed-independent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on ... -
Identifying state coding conflicts in asynchronous system specifications using Petri net unfoldings
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Text en actes de congrés
Accés obertState coding conflict detection is a fundamental part of synthesis of asynchronous concurrent systems from their specifications as signal transition graphs (STGs), which are a special kind of labelled Petri nets. The paper ... -
Improving performance guarantees in wormhole mesh NoC designs
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertWormhole-based mesh Networks-on-Chip (wNoC) are deployed in high-performance many-core processors due to their physical scalability and low-cost. Delivering tight and time composable Worst-Case Execution Time (WCET) estimates ... -
Individual flip-flops with gated clocks for low power datapaths
(Institute of Electrical and Electronics Engineers (IEEE), 1997-06)
Article
Accés obertEnergy consumption has become one of the important factors in digital systems, because of the requirement to dissipate this energy in high-density circuits and to extend the battery life in portable systems such as devices ... -
Logic decomposition of speed-independent circuits
(1999-02)
Article
Accés obertLogic decomposition is a well-known problem in logic synthesis, but it poses new challenges when targeted to speed-independent circuits. The decomposition of a gate into smaller gates must preserve not only the functional ... -
Logic design of asynchronous circuits
(Institute of Electrical and Electronics Engineers (IEEE), 2002)
Text en actes de congrés
Accés obertSummary form only given. This tutorial aims at motivating the audience to consider asynchronous circuits as a competitive alternative to solve some of the design problems inherent to submicron technologies. One of the main ... -
More than Moore. Experience on material implication computing with an electromechanical memristor emulator
(Universitat Politècnica de Catalunya, 2016-09)
Treball Final de Grau
Accés obertEl final de la Ley de Moore es un hecho a tener en cuenta. Quizás, los Nanowire FETs pueden extender la vida del transistor pero no indefinidamente. Es por eso que es necesario encontrar un nuevo dispositivo lógico además ... -
Optimizing CMOS circuits for low power using transistor reordering
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
Text en actes de congrés
Accés obertThis paper addresses the optimization of a circuit for low power using transistor reordering. The optimization algorithm relies on a stochastic model of a static CMOS gate that includes the power internal nodes of the gate. ... -
Partial order based approach to synthesis of speed-independent circuits
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Text en actes de congrés
Accés obertThis paper introduces a novel technique for synthesis of speed-independent circuits from their Signal Transition Graph specifications. The new method uses partial order in the form of the STG-unfolding segment to derive ... -
Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers
(1997-03)
Article
Accés obertPetrify is a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization of asynchronous control circuits. Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition System (TS) it ... -
Polynomial algorithms for the synthesis of hazard-free circuits from signal transition graphs
(Institute of Electrical and Electronics Engineers (IEEE), 1993)
Text en actes de congrés
Accés obertMethods for the synthesis of asynchronous circuits from signal transition graphs (STGs) have commonly used the state graph to solve the two main steps of this process: the state assignment problem and the generation of ... -
Reusing cached schedules in an out-of-order processor with in-order issue logic
(2009)
Text en actes de congrés
Accés obertThe complex and powerful out-of-order issue logic dismisses the repetitive nature of the code, unlike what caches or branch predictors do. We show that 90% of the cycles, the group of instructions selected by the issue ... -
Scheduling and resource binding for low power
(Institute of Electrical and Electronics Engineers (IEEE), 1995)
Text en actes de congrés
Accés obertDecisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during the ... -
State-based encoding of large asynchronous controllers
(Institute of Electrical and Electronics Engineers (IEEE), 2018-09-28)
Article
Accés obertState encoding is one of the fundamental problems in the synthesis of asynchronous controllers. The requirement for a correct hazard-free implementation imposes severe constraints on the way encoding signals can be inserted ... -
Support-reducing decomposition for FPGA mapping
(2020-01)
Article
Accés obertDecomposition is a technology-independent process, in which a large complex function is broken into smaller, less complex functions. The costs of two-level or factored-form representations (cubes and literals) are used in ... -
Synchronous elastic networks
(Institute of Electrical and Electronics Engineers (IEEE), 2006)
Text en actes de congrés
Accés obertWe formally define - at the stream transformer level - a class of synchronous circuits that tolerate any variability in the latency of their environment. We study behavioral properties of networks of such circuits and prove ... -
Synthesis of speed-independent circuits from STG-unfolding segment
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Text en actes de congrés
Accés obertThis paper presents a novel technique for synthesis of speed-independent circuits. It is based on partial order representation of the state graph called STG-unfolding segment. The new method uses approximation technique ... -
Technology mapping for speed-independent circuits: Decomposition and resynthesis
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Text en actes de congrés
Accés obertThis paper presents theory and practical implementation of a method for multi-level logic synthesis of speed-independent circuits. An initial circuit implementation is assumed to satisfy the monotonous cover conditions but ...
